公开(公告)号：US20080061334A1

公开(公告)日：2008-03-13

申请号：US11896952

申请日：2007-09-07

申请人： Ju-Young Jung ,  Suk-Ho Joo ,  Jung-Hoon Park ,  Heung-Jin Joo ,  Hee-San Kim ,  Seung-Kuk Kang ,  Do-Yeon Choi

发明人： Ju-Young Jung ,  Suk-Ho Joo ,  Jung-Hoon Park ,  Heung-Jin Joo ,  Hee-San Kim ,  Seung-Kuk Kang ,  Do-Yeon Choi

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L27/11507 ,  H01L21/76849 ,  H01L21/7687 ,  H01L23/5226 ,  H01L27/11502 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device and a method for forming the same. The method includes forming an insulating layer on a semiconductor substrate having a conductive region, forming a contact hole that exposes the conductive region by etching the insulating layer, forming a barrier metal layer that covers a sidewall and a bottom of the contact hole, and forming a contact plug in the contact hole by interposing the barrier metal layer therebetween. An etching process may be preformed that recesses the barrier metal layer and the contact plug in such a manner that a top surface of the contact plug protrudes upward beyond a top surface of the barrier metal layer. A capping plug may be formed covering the recessed barrier metal layer and the recessed contact plug. A capacitor may be formed on the capping plug.

摘要翻译： 一种半导体存储器件及其形成方法。 该方法包括在具有导电区域的半导体衬底上形成绝缘层，形成通过蚀刻绝缘层而暴露导电区域的接触孔，形成覆盖接触孔的侧壁和底部的阻挡金属层，以及形成 通过在其间插入阻挡金属层，在接触孔中形成接触塞。 可以进行蚀刻工艺，其以使得接触插头的顶表面向上突出超过阻挡金属层的顶表面的方式使阻挡金属层和接触插塞凹陷。 可以形成覆盖凹陷的阻挡金属层和凹入的接触插塞的封盖塞。 可以在封盖上形成电容器。

公开(公告)号：US20080067566A1

公开(公告)日：2008-03-20

申请号：US11797138

申请日：2007-05-01

申请人： Do-Yeon Choi ,  Hee-San Kim ,  Heung-Jin Joo

发明人： Do-Yeon Choi ,  Hee-San Kim ,  Heung-Jin Joo

IPC分类号： H01L23/48 ,  H01L21/00 ,  H01L29/94

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/57

摘要： A ferroelectric memory device may include a substrate, an interlayer insulating layer on the semiconductor substrate, a contact plug penetrating the interlayer insulating layer, the contact plug being formed of a sequentially stacked metal plug and buffer plug, a conductive protection pattern covering the contact plug, the conductive protection pattern being a conductive oxide layer, a lower electrode, a ferroelectric pattern, and an upper electrode sequentially stacked on the conductive protection pattern, and an insulating protection layer covering the sequentially stacked lower electrode, ferroelectric pattern, and upper electrode.

摘要翻译： 铁电存储器件可以包括衬底，半导体衬底上的层间绝缘层，穿透层间绝缘层的接触插塞，接触插塞由顺序堆叠的金属插塞和缓冲插塞形成，覆盖接触插塞的导电保护图案 所述导电保护图案是导电性氧化物层，下部电极，铁电体图案和依次层叠在所述导电性保护图案上的上部电极，所述绝缘保护层覆盖顺序层叠的下部电极，铁电体图案和上部电极。

公开(公告)号：US20080087926A1

公开(公告)日：2008-04-17

申请号：US11853039

申请日：2007-09-11

申请人： Jung-Hoon Park ,  Heung-Jin Joo

发明人： Jung-Hoon Park ,  Heung-Jin Joo

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/57

摘要： A method of forming a ferroelectric random access memory includes sequentially forming a conductive pattern, an etch-stop layer, a ferroelectric capacitor and an interlayer dielectric on a semiconductor substrate, which includes a first region and a second region. The ferroelectric capacitor is formed on the first region and the conductive pattern is formed on the second region. The interlayer dielectric is patterned to simultaneously form a first opening to expose a top surface of the ferroelectric capacitor and a second opening to expose a top surface of the etch-stop layer. The patterned interlayer dielectric is annealed in an ambient atmosphere, including oxygen atoms. The etch-stop layer exposed through the second opening is etched to expose a top surface of the conductive pattern. First and second top plugs are formed to connect to the ferroelectric capacitor and the conductive pattern through the first and second openings, respectively.

摘要翻译： 形成铁电随机存取存储器的方法包括：在包括第一区域和第二区域的半导体衬底上依次形成导电图案，蚀刻停止层，铁电电容器和层间电介质。 铁电电容器形成在第一区域上，导电图案形成在第二区域上。 图案化层间电介质以同时形成第一开口以暴露铁电电容器的顶表面和第二开口以暴露蚀刻停止层的顶表面。 图案化的层间电介质在包括氧原子的环境气氛中退火。 通过第二开口暴露的蚀刻停止层被蚀刻以暴露导电图案的顶表面。 形成第一和第二顶部插头，以分别通过第一和第二开口连接到铁电电容器和导电图案。

公开(公告)号：US07294876B2

公开(公告)日：2007-11-13

申请号：US11325633

申请日：2006-01-03

申请人： Heung-Jin Joo ,  Bon-Jae Koo ,  Jung-Hoon Park

发明人： Heung-Jin Joo ,  Bon-Jae Koo ,  Jung-Hoon Park

IPC分类号： H01L29/76 ,  H01L21/8242

CPC分类号： H01L27/11507 ,  H01L21/76846 ,  H01L21/7687 ,  H01L27/11502 ,  H01L28/57 ,  H01L28/65

摘要： An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

摘要翻译： FeRAM的一个实施例包括具有底部电极，铁电体层和顶部电极的铁电电容器。 在底电极和铁电层之间以及铁电层和顶电极之间形成氧化钌。 包括氧化钌和铱的扩散阻挡层形成在顶部电极和连接到互连铁电电容器的顶部电极的板线的直接电池接触插塞之间。 因此，抑制了在后续工艺中产生的氮或金属材料的扩散以防止铁电层的劣化。

公开(公告)号：US20060157763A1

公开(公告)日：2006-07-20

申请号：US11325633

申请日：2006-01-03

申请人： Heung-Jin Joo ,  Bon-Jae Koo ,  Jung-Hoon Park

发明人： Heung-Jin Joo ,  Bon-Jae Koo ,  Jung-Hoon Park

IPC分类号： H01L29/94 ,  H01L21/00

CPC分类号： H01L27/11507 ,  H01L21/76846 ,  H01L21/7687 ,  H01L27/11502 ,  H01L28/57 ,  H01L28/65

摘要： An embodiment of the FeRAM includes a ferroelectric capacitor including a bottom electrode, a ferroelectric layer, and a top electrode. Strontium ruthenium oxide is formed between the bottom electrode and the ferroelectric layer and between the ferroelectric layer and the top electrode. A diffusion barrier layer including strontium ruthenium oxide and iridium is formed between the top electrode and a direct cell contact plug coupled to a plate line interconnecting top electrodes of ferroelectric capacitors. Thus, diffusion of nitrogen or metallic materials produced in subsequent processes is suppressed to prevent degradation of the ferroelectric layer.

摘要翻译： FeRAM的一个实施例包括具有底部电极，铁电体层和顶部电极的铁电电容器。 在底电极和铁电层之间以及铁电层和顶电极之间形成氧化钌。 包括氧化钌和铱的扩散阻挡层形成在顶部电极和连接到互连铁电电容器的顶部电极的板线的直接电池接触插塞之间。 因此，抑制了在后续工艺中产生的氮或金属材料的扩散以防止铁电层的劣化。

公开(公告)号：US07105418B2

公开(公告)日：2006-09-12

申请号：US10997408

申请日：2004-11-24

申请人： Heung-Jin Joo

发明人： Heung-Jin Joo

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/55

摘要： For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.

摘要翻译： 为了形成叠层电容器，通过至少一种半导体材料形成开口。 在开口内图案化下电极材料，以在开口内形成多个下电极。 堆叠的电容器通过在开口内沉积电容器电介质和上电极而在开口内由下电极形成。 通过这样一个比较大的开口，叠层电容器的电容器电介质被沉积成较大的厚度，以提高叠层电容器的可靠性。

公开(公告)号：US20060006447A1

公开(公告)日：2006-01-12

申请号：US11180954

申请日：2005-07-12

申请人： Hyun-Ho Kim ,  Heung-Jin Joo ,  Ki-Nam Kim

发明人： Hyun-Ho Kim ,  Heung-Jin Joo ,  Ki-Nam Kim

IPC分类号： H01L27/108

CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/91

摘要： A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer on an inner sidewall of an opening exposing the plate electrode by a plasma entire surface anisotropic etching.

公开(公告)号：US20080111171A1

公开(公告)日：2008-05-15

申请号：US11811931

申请日：2007-06-12

申请人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

发明人： Heung-Jin Joo ,  Yoon-Jong Song ,  Ki-Nam Kim

IPC分类号： H01L29/94 ,  H01L21/02

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

摘要： In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.

摘要翻译： 在铁电随机存取存储器件中的电容器下的节点结构及其形成方法中，节点结构的顶表面设置在与节点结构周围的层间绝缘层的顶表面基本相同的水平处，并且 因此可以使电容器中的铁电体的晶体生长稳定。 为此，在半导体衬底上形成节点绝缘图案。 定义节点绝缘图案周围的节点的节点设置在节点绝缘图案之下。 节点导电图案设置在节点限定图案和节点绝缘图案之间。

公开(公告)号：US20070158731A1

公开(公告)日：2007-07-12

申请号：US11620225

申请日：2007-01-05

申请人： Byoung-Jae Bae ,  Byung-Gil Jeon ,  Heung-Jin Joo ,  Dong-Chul Yoo ,  Sang-Don Nam

发明人： Byoung-Jae Bae ,  Byung-Gil Jeon ,  Heung-Jin Joo ,  Dong-Chul Yoo ,  Sang-Don Nam

IPC分类号： H01L29/76

CPC分类号： H01L27/11502 ,  G11C11/22 ,  H01L27/11585 ,  H01L27/1159

摘要： A memory device includes one or more layers of parallel strings of ferroelectric gate transistors on a substrate, each layer of parallel strings including a plurality of parallel line-shaped active regions and a plurality of word lines extending in parallel transversely across the active regions and disposed on ferroelectric patterns on the active regions. A string select gate line may extend transversely across the active regions in parallel with the word lines. A ground select gate line may extend transversely across the active regions in parallel with the word lines.

摘要翻译： 存储器件包括在衬底上的一层或多层平行的铁电栅极晶体管层，每层平行的串包括多个平行的线状有源区和跨越有源区并行延伸的多条字线， 关于活跃区域的铁电模式。 串选择栅极线可以横跨有源区域与字线平行地延伸。 接地选择栅极线可以与字线平行地跨越有源区横向延伸。

公开(公告)号：US07262453B2

公开(公告)日：2007-08-28

申请号：US11496384

申请日：2006-07-31

申请人： Heung-Jin Joo

发明人： Heung-Jin Joo

IPC分类号： H01L21/336

CPC分类号： H01L28/91 ,  H01L27/0207 ,  H01L27/10852 ,  H01L28/55

摘要： For forming stacked capacitors, an opening is formed through at least one semiconductor material. A lower electrode material is patterned within the opening to form a plurality of lower electrodes within the opening. The stacked capacitors are formed with the lower electrodes within the opening by depositing a capacitor dielectric and an upper electrode within the opening. With such a relatively large opening, a capacitor dielectric of the stacked capacitors is deposited with a large thickness for improving reliability of the stacked capacitors.

摘要翻译： 为了形成叠层电容器，通过至少一种半导体材料形成开口。 在开口内图案化下电极材料，以在开口内形成多个下电极。 堆叠的电容器通过在开口内沉积电容器电介质和上电极而在开口内由下电极形成。 通过这样一个比较大的开口，叠层电容器的电容器电介质被沉积成较大的厚度，以提高叠层电容器的可靠性。