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    Large scale integrated circuit for low voltage operation
    2.
    发明授权
    Large scale integrated circuit for low voltage operation 失效
    用于低压运行的大规模集成电路

    公开(公告)号：US5262999A

    公开(公告)日：1993-11-16

    申请号：US838505

    申请日：1992-03-24

    申请人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    发明人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/00

    CPC分类号： G11C5/147 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096

    摘要： Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

    摘要翻译： 公开了一种单芯片ULSI，其可以在宽范围的电源电压（1V至5.5V）中进行固定操作。 该单芯片ULSI由一个电压转换器电路组成，该电路用于宽范围电源电压的固定内部电压，可适用于多个输入/输出电平的输入/输出缓冲器，一个动态RAM 可以在2V以下的电源电压下工作的这种单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本， 固态摄像机等

    Large scale integrated circuit for low voltage operation
    3.
    发明授权
    Large scale integrated circuit for low voltage operation 失效
    用于低压运行的大规模集成电路

    公开(公告)号：US5297097A

    公开(公告)日：1994-03-22

    申请号：US366869

    申请日：1989-06-14

    申请人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    发明人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/407

    CPC分类号： G11C11/4096 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/147

    摘要： Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power supply voltages, an input/output buffer which can be adapted to several input/out interface levels, a dynamic or volatile RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

    摘要翻译： 公开了一种单芯片ULSI，其可以对宽范围的电源电压（1V至5.5V）进行固定操作。 该单芯片ULSI由一个电压转换器电路组成，该电路为广泛的电源电压提供固定的内部电压，可适应多个输入/输出接口电平的输入/输出缓冲器，动态或 可以在2V以下的电源电压下工作的易失性RAM。该单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本 ，固态摄像机等

    Large scale integrated circuit with sense amplifier circuits for low voltage operation
    4.
    再颁专利
    Large scale integrated circuit with sense amplifier circuits for low voltage operation 失效
    具有读出放大器电路的大规模集成电路用于低电压操作

    公开(公告)号：USRE37593E1

    公开(公告)日：2002-03-19

    申请号：US09095101

    申请日：1998-06-10

    申请人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    发明人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    IPC分类号： G11C700

    CPC分类号： G11C11/4096 ,  G11C5/147 ,  G11C11/406 ,  G11C11/4074

    摘要： Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

    摘要翻译： 公开了一种单芯片ULSI，其可以在宽范围的电源电压（1V至5.5V）中进行固定操作。 该单芯片ULSI由一个电压转换器电路组成，该电路用于宽范围电源电压的固定内部电压，可适用于多个输入/输出电平的输入/输出缓冲器，一个动态RAM 可以在2V以下的电源电压下工作的这种单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本， 固态摄像机等

    Dynamic type semiconductor monolithic memory
    6.
    发明授权
    Dynamic type semiconductor monolithic memory 失效
    动态型半导体单片存储器

    公开(公告)号：US4503522A

    公开(公告)日：1985-03-05

    申请号：US358678

    申请日：1982-03-16

    申请人： Jun Etoh ,  Yoshiki Kawajiri ,  Ryoichi Hori ,  Kiyoo Itoh

    发明人： Jun Etoh ,  Yoshiki Kawajiri ,  Ryoichi Hori ,  Kiyoo Itoh

    IPC分类号： G11C11/408 ,  G11C11/4096 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C11/4085 ,  G11C11/4096

    摘要： A dynamic type semiconductor memory using MOS transistors, in which first and second booster circuits utilizing capacitances, respectively, are provided at each of stages preceding and succeeding to a word driver, respectively. Data lines of the memory are each provided with a voltage compensating circuit for increasing a voltage for charging a memory cell to a level higher than a source voltage for being rewritten in the memory cell. A first boosting circuit is operated after a word line driving pulse signal is produced. Subsequently, word driver selecting transistors are turned off, which is followed by operation of the second booster circuit. Thus, the word line voltage is boosted twice.

    摘要翻译： 使用MOS晶体管的动态型半导体存储器，其中分别在字驱动器之前和之后的每个级提供利用电容的第一和第二升压电路。 存储器的数据线各自设置有电压补偿电路，用于将用于将存储器单元充电的电压提高到高于用于在存储器单元中重写的源电压的电平。 在产生字线驱动脉冲信号之后，第一升压电路被操作。 随后，字驱动器选择晶体管截止，其后是第二升压电路的操作。 因此，字线电压被提升两次。

    Semiconductor memory
    7.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4475181A

    公开(公告)日：1984-10-02

    申请号：US337099

    申请日：1982-01-05

    申请人： Jun Etoh ,  Ryoichi Hori ,  Yoshiki Kawajiri ,  Kiyoo Itoh

    发明人： Jun Etoh ,  Ryoichi Hori ,  Yoshiki Kawajiri ,  Kiyoo Itoh

    IPC分类号： G11C8/00 ,  G11C8/06 ,  G11C8/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/418 ,  H03K5/135 ,  G11C7/00

    CPC分类号： H03K5/135 ,  G11C11/407 ,  G11C11/408 ,  G11C11/418 ,  G11C8/06 ,  G11C8/18

    摘要： A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select one of memory cells. The semiconductor memory is equipped with address buffers exclusively for column and row addressing operations, respectively, the outputs of which are consecutively transmitted to column decoders and row decoders through common internal address lines.

    摘要翻译： 多路复用地址输入的半导体存储器用于通过公共外部地址线接收列地址和行地址，并且响应于第一和第二选通信号连续解码它们，从而选择一个存储单元。 半导体存储器分别配备有用于列和行寻址操作的地址缓冲器，它们的输出通过公共内部地址线连续发送到列解码器和行解码器。

    Semiconductor integrated circuit device comprising a memory array and a processing circuit
    9.
    发明授权
    Semiconductor integrated circuit device comprising a memory array and a processing circuit 失效
    包括存储器阵列和处理电路的半导体集成电路器件

    公开(公告)号：US06205556B1

    公开(公告)日：2001-03-20

    申请号：US09198658

    申请日：1998-11-24

    申请人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

    发明人： Takao Watanabe ,  Katsutaka Kimura ,  Kiyoo Itoh ,  Yoshiki Kawajiri

    IPC分类号： G06F126

    CPC分类号： G06N3/063

    摘要： Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system for the neural network processing. The neural network processing system according to the present invention comprises: a memory circuit for storing neuron output values, connection weights, the desired values of outputs, and data necessary for learning; an input/output circuit for writing or reading data in or out of said memory circuit; a processing circuit for performing a processing for determining the neuron outputs such as the product, sum and nonlinear conversion of the data stored in said memory circuit, a comparison of the output value and its desired value, and a processing necessary for learning; and a control circuit for controlling the operations of said memory circuit, said input/output circuit and said processing circuit. The processing circuit is constructed to include at least one of an adder, a multiplier, a nonlinear transfer function circuit and a comparator so that at least a portion of the processing necessary for determining the neutron output values such as the product or sum may be accomplished in parallel. Moreover, these circuits are shared among a plurality of neutrons and are operated in a time sharing manner to determine the plural neuron output values. Still moreover, the aforementioned comparator compares the neuron output value determined and the desired value of the output in parallel.

    摘要翻译： 这里公开了一种数据处理系统，其中封装有用于实现大规模和高速并行分布式处理的存储器，特别是用于神经网络处理的数据处理系统。 根据本发明的神经网络处理系统包括：存储电路，用于存储神经元输出值，连接权重，输出的期望值和学习所需的数据; 用于将数据写入或读出所述存储电路的输入/输出电路; 用于执行用于确定诸如存储在所述存储器电路中的数据的乘积，和和非线性转换的神经元输出，输出值与其期望值的比较以及学习所需的处理的处理的处理电路; 以及用于控制所述存储电路，所述输入/输出电路和所述处理电路的操作的控制电路。 处理电路被构造为包括加法器，乘法器，非线性传递函数电路和比较器中的至少一个，使得可以实现用于确定诸如乘积或和的中子输出值所需的处理的至少一部分 在平行下。 此外，这些电路在多个中子之间共享并且以分时方式操作以确定多个神经元输出值。 此外，上述比较器并行地比较所确定的神经元输出值和输出的期望值。