公开(公告)号：US6147529A

公开(公告)日：2000-11-14

申请号：US207472

申请日：1998-12-08

Applicant: Jun-Lin Yeh ,  Chien-Chung Chen

Inventor： Jun-Lin Yeh ,  Chien-Chung Chen

IPC: G05F3/24 ,  H03K5/08 ,  H03K17/22 ,  H03K5/22

CPC classification number: H03K17/223 ,  G05F3/242 ,  H03K5/08

Abstract: A voltage sensing circuit consists of a sensing node, a transistor of a first conductivity type, a diode-like device, a first reference voltage source, a transistor of a second conductivity type, and a second reference voltage source. The transistor of a first conductivity type is configured with one source/drain receiving an input voltage signal and another source/drain connected to the sensing node. The diode-like device receives the input voltage signal and, accordingly, generates a voltage-dropped signal. The first reference voltage source is connected to a gate of the transistor of the first conductivity type. The transistor of a second conductivity type is configured with one source/drain connected to the sensing node and a gate receiving the voltage-dropped signal. The second reference voltage source is connected to another source/drain of the transistor of the second conductivity type.

Abstract translation: 电压感测电路由感测节点，第一导电类型的晶体管，二极管类器件，第一参考电压源，第二导电类型的晶体管和第二参考电压源组成。 第一导电类型的晶体管配置有接收输入电压信号的一个源极/漏极和连接到感测节点的另一个源极/漏极。 二极管状器件接收输入电压信号，因此产生降压信号。 第一参考电压源连接到第一导电类型的晶体管的栅极。 第二导电类型的晶体管配置有连接到感测节点的一个源极/漏极和接收电压下降信号的栅极。 第二参考电压源连接到第二导电类型晶体管的另一个源极/漏极。

公开(公告)号：US20120246384A1

公开(公告)日：2012-09-27

申请号：US13053194

申请日：2011-03-21

Applicant: Chi-Cheng Lin ,  Jun-Lin Yeh

Inventor： Chi-Cheng Lin ,  Jun-Lin Yeh

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/0757 ,  G06F11/1417

Abstract: A flash memory accessing method is provided. The method includes: firstly, dividing the flash memory into a primary storage area and a backup storage area, wherein the difference between a first start address of the primary storage area and a second start address of the backup storage area is an offset address not equal to zero; reading the flash memory according to a address pointer equal to the first start address so as to obtain the boot data; making the electronic apparatus perform a boot sequence according to the boot data; then, detecting whether the boot sequence is normal or not, and when the boot sequence is abnormal, providing the flash memory with changing the read pointer to the second start address according to an offset address to read the backup boot data.

Abstract translation: 提供闪速存取存取方法。 该方法包括：首先将闪存分为主存储区和备份存储区，其中主存储区的第一起始地址与备份存储区的第二起始地址之间的差是偏移地址不等于 到零 根据等于第一起始地址的地址指针读取闪存，以获得引导数据; 使电子装置根据引导数据执行引导顺序; 然后，检测引导顺序是否正常，并且当引导顺序异常时，根据偏移地址提供将读指针改变到第二起始地址的闪存，以读取备份引导数据。

公开(公告)号：US08193586B2

公开(公告)日：2012-06-05

申请号：US12389535

申请日：2009-02-20

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang ,  Chien-Liang Chen

IPC: H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US08404572B2

公开(公告)日：2013-03-26

申请号：US12370746

申请日：2009-02-13

Applicant: Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

IPC: H01L21/425

CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract translation: 一种装置包括被配置为执行离子注入工艺的处理室。 在处理室内设有冷却台板或静电吸盘。 冷却台板或静电卡盘构造成支撑半导体晶片。 冷却台板或静电卡盘具有多个温度区域。 每个温度区域包括在冷却压板或静电卡盘内或附近的至少一个流体导管。 提供至少两个冷却剂源，每个冷却剂源流体耦合到相应的一个流体导管，并且构造成在离子注入过程期间将分别不同的冷却剂供应到多个温度区中的相应的一个温度区。 冷却剂源分别包括不同的冷却或制冷装置。

公开(公告)号：US20120221766A1

公开(公告)日：2012-08-30

申请号：US13034683

申请日：2011-02-24

Applicant: Jun-Lin Yeh ,  Chi-Cheng Lin

Inventor： Jun-Lin Yeh ,  Chi-Cheng Lin

IPC: G06F12/00

CPC classification number: G06F9/30043 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/7206 ,  G11C16/20 ,  G11C16/22 ,  G11C2216/30

Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal.

Abstract translation: 公开了具有串行接口的闪存装置。 闪存装置包括选择器，核心电路和可编程数据组。 选择器决定是否将写保护引脚和保持引脚之一连接到复位信号线。 核心电路接收由复位信号线发送的复位信号，并相应地启动复位操作。 通过编程方法将选择数据写入可编程数据库，并且可编程数据组输出选择数据以用作选择信号。

公开(公告)号：US07203107B2

公开(公告)日：2007-04-10

申请号：US11306381

申请日：2005-12-27

Applicant: Jun-Lin Yeh

Inventor： Jun-Lin Yeh

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/883 ,  G11C29/88

Abstract: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.

Abstract translation: 提供一种适用于半导体存储器的用于补偿半导体存储器缺陷的装置。 该装置包括具有至少一个无缺陷的子存储器区域的存储器阵列，该存储器阵列耦合到地址解码器电路和用于存储数据的感测电路。 选择电路耦合到控制单元并将选择信号输出到控制单元。 第一输入地址缓冲器耦合到控制单元和地址解码器电路，并且响应于用于选择无缺陷子存储器区域以存储数据的选择信号而将地址信号输出到地址解码器电路。 还提供了一种用于补偿半导体存储器缺陷的方法，包括确定半导体存储器的存储区是否具有缺陷; 以及当半导体存储器有缺陷时用无缺陷子存储器区域替换存储区域以存储数据。

公开(公告)号：US08914569B2

公开(公告)日：2014-12-16

申请号：US13034683

申请日：2011-02-24

Applicant: Jun-Lin Yeh ,  Chi-Cheng Lin

Inventor： Jun-Lin Yeh ,  Chi-Cheng Lin

IPC: G06F12/00 ,  G06F12/02 ,  G11C16/20 ,  G11C16/22

CPC classification number: G06F9/30043 ,  G06F12/00 ,  G06F12/0246 ,  G06F2212/7206 ,  G11C16/20 ,  G11C16/22 ,  G11C2216/30

Abstract: A flash memory apparatus with serial interface is disclosed. The flash memory apparatus includes a selector, a core circuit and a programmable data bank. The selector decides whether or not to connect one of a write protect pin and a hold pin to a reset signal line. The core circuit receives a reset signal transmitted by the reset signal line and activates a reset operation accordingly. A selecting data is written into the programmable data bank through a programming method and the programmable data bank outputs the selecting data to serve as a selecting signal.

Abstract translation: 公开了具有串行接口的闪存装置。 闪存装置包括选择器，核心电路和可编程数据组。 选择器决定是否将写保护引脚和保持引脚之一连接到复位信号线。 核心电路接收由复位信号线发送的复位信号，并相应地启动复位操作。 通过编程方法将选择数据写入可编程数据库，并且可编程数据组输出选择数据以用作选择信号。

公开(公告)号：US08450161B2

公开(公告)日：2013-05-28

申请号：US13465551

申请日：2012-05-07

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC: H01L21/00 ,  H01L21/02

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20100044803A1

公开(公告)日：2010-02-25

申请号：US12389535

申请日：2009-02-20

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yi Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20060203579A1

公开(公告)日：2006-09-14

申请号：US11306381

申请日：2005-12-27

Applicant: Jun-Lin Yeh

Inventor： Jun-Lin Yeh

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/883 ,  G11C29/88

Abstract: A device for compensating a semiconductor memory defect, suitable for use in a semiconductor memory, is provided. The device includes a memory array, having at least a defectless sub-memory region, the memory array being coupled to an address decoder circuit and a sensing circuit for storing data. A selection circuit is coupled to a control unit and outputs a selection signal to the control unit. A first input address buffer is coupled to the control unit and the address decoder circuit, and outputs an address signal to the address decoder circuit in response to the selection signal for selecting the defectless sub-memory region to store data. A method for compensating a semiconductor memory defect is also provided, including determining whether the memory region of the semiconductor memory has a defect; and replacing the memory region with the defectless sub-memory region to store data when the semiconductor memory is defective.

Abstract translation: 提供一种适用于半导体存储器的用于补偿半导体存储器缺陷的装置。 该装置包括具有至少一个无缺陷的子存储器区域的存储器阵列，该存储器阵列耦合到地址解码器电路和用于存储数据的感测电路。 选择电路耦合到控制单元并将选择信号输出到控制单元。 第一输入地址缓冲器耦合到控制单元和地址解码器电路，并且响应于用于选择无缺陷子存储器区域以存储数据的选择信号而将地址信号输出到地址解码器电路。 还提供了一种用于补偿半导体存储器缺陷的方法，包括确定半导体存储器的存储区是否具有缺陷; 以及当半导体存储器有缺陷时用无缺陷子存储器区域替换存储区域以存储数据。