公开(公告)号：US08929171B2

公开(公告)日：2015-01-06

申请号：US13571486

申请日：2012-08-10

申请人： June-Hong Park ,  Jin-Yub Lee

发明人： June-Hong Park ,  Jin-Yub Lee

IPC分类号： G11C11/4193 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  G11C8/10

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C8/10 ,  G11C16/04 ,  G11C16/30

摘要： A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied.

摘要翻译： 非易失性存储器件包括电压供应控制器（VSC），用于检测电源电压的电平并响应于此产生第一内部电压。 当电源电压正常提供时，VSC提供等于外部高电压的第一内部电压，但是当电源电压异常供给时，VSC将第一内部电压提供到低于外部高电压的电平。

公开(公告)号：US07489565B2

公开(公告)日：2009-02-10

申请号：US11762797

申请日：2007-06-14

申请人： Ji-Ho Cho ,  Soo-Han Kim ,  June-Hong Park

发明人： Ji-Ho Cho ,  Soo-Han Kim ,  June-Hong Park

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C16/10 ,  G11C2207/104 ,  G11C2216/14

摘要： A flash memory device includes a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits includes a plurality of registers which store two corresponding data bits among the at least 2-word data, respectively and scan logics corresponding to the registers, respectively, which scan a number of program data of a first word data among the at least 2-word data during a first scan interval, and which scan a number of program data of a second word data among the at least 2-word data based on the number of the program data of the first word data during a second scan interval.

摘要翻译： 闪速存储器件包括存储单元阵列和临时存储要存储在存储单元阵列中的程序数据的多缓冲块，其中多缓冲块包括存储至少2个字的多个缓冲电路 数据。 每个缓冲电路包括多个寄存器，分别在至少2个字数据中存储两个相应的数据位，分别扫描对应于寄存器的逻辑，扫描逻辑数据中的第一个字数据的多个节目数据 在第一扫描间隔期间的至少2字数据，并且在第二扫描期间，基于第一字数据的节目数据的数目，扫描至少2个字数据中的第二字数据的数目的数目 间隔。

公开(公告)号：US10090046B2

公开(公告)日：2018-10-02

申请号：US15341253

申请日：2016-11-02

申请人： Sang-Soo Park ,  June-Hong Park ,  Dongkyo Shim

发明人： Sang-Soo Park ,  June-Hong Park ,  Dongkyo Shim

IPC分类号： G11C11/34 ,  G11C11/56 ,  G11C16/28 ,  G11C16/10 ,  G11C16/08 ,  G11C29/02 ,  G11C29/52

摘要： Disclosed is a nonvolatile memory device. The nonvolatile memory device includes a cell array including a plurality of memory cells, a page buffer including a plurality of latch sets, and a control logic. The page buffer is connected to the cell array through bit lines. The latch sets respectively are configured to sense data from selected memory cells among the memory cells through the bit lines. The latch sets respectively are configured to perform a plurality of read operations to determine one data state. The latch sets are respectively configured to store results of the read operations. The control logic configured to control the page buffer such that the latch sets sequentially and respectively store the results of the read operations, to compare data stored in the latch sets with each other, and to select one latch set among the latch sets based on the comparison result.