公开(公告)号：US20120170366A1

公开(公告)日：2012-07-05

申请号：US13337196

申请日：2011-12-26

Applicant: Ji Hwan KIM ,  Seong Je PARK ,  Jung Hwan LEE ,  Myung CHO ,  Beom Seok HAH

Inventor： Ji Hwan KIM ,  Seong Je PARK ,  Jung Hwan LEE ,  Myung CHO ,  Beom Seok HAH

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/565

Abstract: A method of operating a semiconductor memory device includes performing a first program loop including a first program operation and a first verification operation in order to store a lower bit data of n-bit data in memory cells coupled to a page, performing a subprogram loop for memory cells of an erase state, having threshold voltages lower than a target voltage of a negative potential, so that the threshold voltages of the memory cells of the erase state become higher than the target voltage, and performing a second program loop including a second program operation and a second verification operation in order to store an upper bit data of the n-bit data in the memory cells.

Abstract translation: 一种操作半导体存储器件的方法包括执行包括第一程序操作和第一验证操作的第一程序循环，以便将n位数据的低位数据存储在耦合到页面的存储单元中，执行子程序循环 具有低于负电位的目标电压的阈值电压的擦除状态的存储单元，使得擦除状态的存储单元的阈值电压变得高于目标电压，并且执行包括第二程序的第二程序循环 操作和第二验证操作，以便将n位数据的高位数据存储在存储单元中。

公开(公告)号：US20080180264A1

公开(公告)日：2008-07-31

申请号：US11679944

申请日：2007-02-28

Applicant: Jung Hwan LEE ,  Grant EO

Inventor： Jung Hwan LEE ,  Grant EO

IPC: G05F1/10 ,  G08B21/00

CPC classification number: H02J7/0031

Abstract: The present invention relates to a power control apparatus and method for preventing a system from being repeatedly booted and shut off by re-setting a cut-off voltage when the system is shut down by a cutoff mode. The power control apparatus of a terminal device according to the present invention comprises a power controller 30 for controlling power supplied from a battery 10 to the terminal device; and a memory 60 for storing a cutoff voltage value for shutting down a system if a voltage of the battery 10 is lower than a reference value, wherein the power controller 30 sets a flag when the system is shut down by a cutoff mode. When the system is rebooted, it is determined whether to drive the system based on an additional cutoff voltage, if the flag is set. According to the present invention, it is possible to prevent the system from being shut down by the cutoff mode after it has been driven. Therefore, there is an advantage in that the life span of the battery can be extended and the charging time of the battery can be saved.

Abstract translation: 本发明涉及一种电源控制装置和方法，用于当通过截止模式关闭系统时，通过重新设置截止电压来防止系统被重新启动和关闭。 根据本发明的终端装置的电力控制装置包括：电源控制器30，用于控制从电池10向终端装置供电的电力; 以及存储器60，用于如果电池10的电压低于参考值，则存储用于关闭系统的截止电压值，其中当系统通过截止模式关闭时，功率控制器30设置标志。 当系统重新启动时，如果标志被设置，则确定是否基于附加的截止电压来驱动系统。 根据本发明，可以防止系统在被驱动之后被截止模式关闭。 因此，可以延长电池的寿命并节省电池的充电时间。

公开(公告)号：US20080052477A1

公开(公告)日：2008-02-28

申请号：US11559298

申请日：2006-11-13

Applicant: Jung Hwan LEE ,  Jung Hwan SO

Inventor： Jung Hwan LEE ,  Jung Hwan SO

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G06F12/127 ,  G06F12/0871 ,  G06F2212/222 ,  Y02D10/13

Abstract: Access to non-volatile memory is controlled when a first data segment is loaded in the non-volatile memory from a hard disk, a weight is calculated for the first data segment stored in the non-volatile memory based on at least one of the access frequency, the access recency, and the size of the first data segment, and the calculated weight is stored in a weight table. A removal rank is calculated for the first data segment based on at least one weight stored in the weight table, a determination is made as to whether a storage capacity of the non-volatile memory is utilized above a predetermined threshold, and a data segment is removed from the non-volatile memory based on a removal rank associated with the data segment.

Abstract translation: 当从硬盘将第一数据段加载到非易失性存储器中时，控制对非易失性存储器的访问，基于存取在非易失性存储器中的至少一个访问来计算针对存储在非易失性存储器中的第一数据段的权重 频率，访问新近度和第一数据段的大小，并且计算的权重存储在权重表中。 基于存储在权重表中的至少一个权重，针对第一数据段计算删除等级，确定非易失性存储器的存储容量是否高于预定阈值，并且数据段是 基于与数据段相关联的移除等级从非易失性存储器中移除。

公开(公告)号：US20080007221A1

公开(公告)日：2008-01-10

申请号：US11564387

申请日：2006-11-29

Applicant: Jung Hwan LEE

Inventor： Jung Hwan LEE

IPC: H02J7/00

CPC classification number: G01R31/3648

Abstract: Enhanced-accuracy battery capacity prediction in which a residual capacity of a battery associated with a mobile electronic device are determined and displayed. One or more characteristic values of the battery are detected and an appropriate battery discharge curve is selected from multiple stored battery discharge curves based on the electrical current supply rate or a number of historical charge/discharge cycles of the battery, or both. A detected battery voltage is compared to the selected curve, and the residual capacity of the battery is calculated based on the present discharge capacity and the useful discharge capacity of the battery based on the selected curve. The residual capacity accurately reflects the present operational state of the device and the present state of the battery. The accurate residual capacity of the battery is displayed on a display device for user viewing.

Abstract translation: 确定并显示与移动电子设备相关联的电池的剩余容量的增强精度的电池容量预测。 检测电池的一个或多个特征值，并且基于电流供给速率或电池的历史充电/放电循环的数量，或两者，从多个存储的电池放电曲线中选择适当的电池放电曲线。 将检测到的电池电压与所选择的曲线进行比较，并且基于当前放电容量和基于所选曲线的电池的有用放电容量来计算电池的剩余容量。 剩余容量准确地反映了设备的当前操作状态和电池的当前状态。 电池的精确剩余容量显示在用于观看的显示装置上。

公开(公告)号：US20120060056A1

公开(公告)日：2012-03-08

申请号：US13225621

申请日：2011-09-06

Applicant: Jung Hwan LEE ,  Seong Je PARK

Inventor： Jung Hwan LEE ,  Seong Je PARK

IPC: H03M13/09 ,  G06F11/10 ,  H03M13/05

CPC classification number: G11C16/3459 ,  G06F11/1048 ,  G11C16/0483 ,  G11C16/10

Abstract: A method of operating a semiconductor memory device according to an aspect of the present disclosure includes performing a program loop, including a program operation and a program verification operation, in order to store input data in selected memory cells, performing a first error bit check operation for comparing the number of error bits of data not identical with the input data, with the number of correctable error bits, if the number of error bits is equal to or smaller than the number of correctable error bits, performing a second error bit check operation for comparing the number of error bits with the reference number of bits for replacement determination, and if the number of error bits is greater than the reference number of bits for replacement determination, updating failed column address information by adding the column address of a memory cell, having the error bits, to the failed column address information.

Abstract translation: 根据本公开的一个方面的操作半导体存储器件的方法包括执行包括程序操作和程序验证操作的程序循环，以便将输入数据存储在所选择的存储器单元中，执行第一错误位检查操作 用于将与输入数据不同的数据的错误位的数量与可校正错误位的数量进行比较，如果错误位的数量等于或小于可校正错误位的数量，则执行第二错误位检查操作 用于将错误位数与用于替换确定的参考位数进行比较，并且如果错误位的数量大于用于替换确定的参考位数，则通过将存储器单元的列地址相加来更新故障列地址信息 具有错误位，失败的列地址信息。

公开(公告)号：US20110253941A1

公开(公告)日：2011-10-20

申请号：US13172348

申请日：2011-06-29

Applicant: Seon Mi YOON ,  Hyeon Jin SHIN ,  Jae Young CHOI ,  Seong Jae CHOI ,  Bum Jae LEE ,  Ungyu PAIK ,  Sangkyu LEE ,  Jung Hwan LEE

Inventor： Seon Mi YOON ,  Hyeon Jin SHIN ,  Jae Young CHOI ,  Seong Jae CHOI ,  Bum Jae LEE ,  Ungyu PAIK ,  Sangkyu LEE ,  Jung Hwan LEE

IPC: C09K11/06

CPC classification number: C08F265/00 ,  C08F20/10 ,  C08F265/04 ,  C08K5/0041 ,  C08L33/14 ,  C08L51/003 ,  C08L53/00 ,  C09K11/02 ,  C09K11/08 ,  C08L2666/02

Abstract: Disclosed is a dispersant having a multifunctional head, and a phosphor paste composition comprising the dispersant. The dispersant has a multifunctional head that comprises an acidic group, a basic group and an aromatic group, thereby enhancing an affinity for the surface of phosphor particles and improving dispersibility.

公开(公告)号：US20190043880A1

公开(公告)日：2019-02-07

申请号：US15928559

申请日：2018-03-22

Applicant: Jung Hwan LEE ,  Jee Yong KIM ,  Seok Jung YUN ,  Ji Hyeon LEE

Inventor： Jung Hwan LEE ,  Jee Yong KIM ,  Seok Jung YUN ,  Ji Hyeon LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction.

公开(公告)号：US20120236618A1

公开(公告)日：2012-09-20

申请号：US13420038

申请日：2012-03-14

Applicant: Jung Hwan LEE ,  Seong Je PARK ,  Ji Hwan KIM ,  Myung CHO ,  Beom Seok HAH

Inventor： Jung Hwan LEE ,  Seong Je PARK ,  Ji Hwan KIM ,  Myung CHO ,  Beom Seok HAH

IPC: G11C15/00

CPC classification number: G11C15/046 ,  G11C16/10

Abstract: A semiconductor memory device includes a memory array configured to include memory cells for storing input data and Code Address Memory (CAM) cells for storing setting data used to set an operation condition; an operation circuit configured to perform a CAM read operation by supplying a read voltage to the CAM cells, perform a test operation for detecting unstable CAM cells in each of which a difference between a threshold voltage and the read voltage is smaller than a permitted limit, from among the CAM cells, and perform an erase operation or a program operation for the unstable CAM cells; and a controller configured to control the operation circuit so that the program operation for storing the setting data in the unstable CAM cells is performed if the number of unstable CAM cells detected in the test operation is greater than a permitted value.

Abstract translation: 半导体存储器件包括：存储器阵列，被配置为包括用于存储输入数据的存储器单元和用于存储用于设置操作条件的设置数据的代码地址存储器（CAM）单元; 配置为通过向CAM单元提供读取电压来执行CAM读取操作的操作电路，执行用于检测阈值电压和读取电压之间的差小于允许极限的不稳定的CAM单元的测试操作， 从CAM单元中进行擦除操作或对不稳定的CAM单元的编程动作; 以及控制器，其被配置为如果在测试操作中检测到​​的不稳定的CAM单元的数量大于允许值，则执行用于将设置数据存储在不稳定的CAM单元中的程序操作。

公开(公告)号：US20120057409A1

公开(公告)日：2012-03-08

申请号：US13183675

申请日：2011-07-15

Applicant: Jung Hwan LEE ,  Seong Je PARK

Inventor： Jung Hwan LEE ,  Seong Je PARK

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells, precharging bit lines coupled to undetermined memory cells whose data has not been determined by the first read operation, and performing a second read operation by supplying a second reference voltage to the memory cells in order to determine data stored in the undetermined memory cells.

Abstract translation: 根据本公开的示例性实施例的非易失性存储器件的读取方法包括预先充电与存储器单元耦合的位线，通过向存储器单元提供第一参考电压来执行第一读取操作，以便确定存储在存储器中的数据 单元，预充电位线，其耦合到其数据尚未被第一读取操作确定的未确定存储单元，以及通过向存储器单元提供第二参考电压来执行第二读取操作，以便确定存储在未确定的存储器单元中的数据。

公开(公告)号：US20120008416A1

公开(公告)日：2012-01-12

申请号：US13177764

申请日：2011-07-07

Applicant: Myung CHO ,  Hwang HUH ,  Jung Hwan LEE ,  Ji Hwan KIM

Inventor： Myung CHO ,  Hwang HUH ,  Jung Hwan LEE ,  Ji Hwan KIM

IPC: G11C16/10 ,  G11C16/06

CPC classification number: G11C16/26 ,  G11C16/10 ,  G11C29/1201 ,  G11C29/50 ,  G11C2029/5006 ,  G11C2216/14

Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of cell strings and a page buffer group comprising a plurality of page buffers coupled to the respective cell string through bit lines. Each of the page buffers includes a latch unit for storing data to be programmed into memory cells included in the cell string or for storing data read from the memory cells. Each of the page buffers is coupled to a pad for the test operation of the memory cells according to data stored in the latch unit in the test operation.

Abstract translation: 半导体存储器件包括包括多个单元串的存储单元阵列和包括通过位线耦合到各个单元串的多个页缓冲器的页缓冲器组。 每个页面缓冲器包括用于存储要被编程到包括在单元串中的存储器单元中的数据或用于存储从存储器单元读取的数据的锁存单元。 根据在测试操作中存储在锁存单元中的数据，每个页缓冲器被耦合到用于存储器单元的测试操作的焊盘。