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公开(公告)号：US20130208533A1
公开(公告)日：2013-08-15
申请号：US13372099
申请日：2012-02-13
CPC分类号： G11C11/4094 , G11C11/419
摘要： A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.
摘要翻译： 存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。 读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。 读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。 读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。
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公开(公告)号：US20130194877A1
公开(公告)日：2013-08-01
申请号：US13362847
申请日：2012-01-31
CPC分类号： G11C7/12 , G11C7/106 , G11C7/1087 , G11C7/18 , G11C11/419 , G11C2207/005
摘要： A memory includes a plurality of memory blocks, a plurality of global bit lines, a common pre-charging circuit, and a selection circuit. Each memory block includes a pair of bit lines, and a plurality of memory cells coupled to the pair of bit lines. Each global bit line is coupled to at least one of the memory blocks. The pre-charging circuit is configured to pre-charge the global bit lines, one at a time, to a pre-charge voltage. The selection circuit is coupled between the pre-charging circuit and the global bit lines, and configured to couple the global bit lines, one at a time, to the pre-charging circuit.
摘要翻译： 存储器包括多个存储器块，多个全局位线，公共预充电电路和选择电路。 每个存储块包括一对位线和耦合到该对位线的多个存储器单元。 每个全局位线耦合到至少一个存储器块。 预充电电路被配置为将全局位线一次一个地预充电到预充电电压。 选择电路耦合在预充电电路和全局位线之间，并且被配置为将全局位线一次一个地耦合到预充电电路。
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公开(公告)号：US20130128655A1
公开(公告)日：2013-05-23
申请号：US13303231
申请日：2011-11-23
CPC分类号： G11C8/10 , G11C11/413 , G11C11/418
摘要： An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.
摘要翻译： 一种装置包括电平移位器和开关电路。 电平移位器包括具有与第一输出的逻辑值互补的逻辑值的输入，第一输出和第二输出。 切换电路包括数据输入，耦合到电平移位器的第二输出的反馈输入以及耦合到电平移位器的输入的输出。 开关电路被配置为基于选择信号选择性地锁存第二输出处的电平移位器的逻辑状态。
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公开(公告)号：US20140269110A1
公开(公告)日：2014-09-18
申请号：US13837614
申请日：2013-03-15
申请人： Jung-Ping YANG , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU , Cheng Hung LEE
发明人： Jung-Ping YANG , Chia-En HUANG , Fu-An WU , Chih-Chieh CHIU , Cheng Hung LEE
CPC分类号： G11C7/065 , G06F17/5063 , G06F17/5081 , G11C7/1048 , G11C7/12 , G11C11/419
摘要： A sensing amplifier for a memory device includes first and second nodes, an input device and an output device. The memory device includes first and second bit lines, and at least one memory cell coupled to the bit lines. The first and second nodes are coupled to the first and second bit lines, respectively. The input device is coupled to the first and second nodes and generates a first current pulling the first node toward a predetermined voltage in response to a first datum read out from the memory cell, and to generate a second current pulling the second node toward the predetermined voltage in response to a second datum read out from the memory cell. The output device is coupled to the first node to output the first or second datum read out from the memory cell. The first current is greater than the second current.
摘要翻译： 用于存储器件的感测放大器包括第一和第二节点，输入设备和输出设备。 存储器件包括第一和第二位线，以及耦合到位线的至少一个存储器单元。 第一和第二节点分别耦合到第一和第二位线。 输入设备耦合到第一和第二节点，并且响应于从存储器单元读出的第一数据产生第一电流将第一节点拉向预定电压，并且产生将第二节点拉向预定的第二电流的第二电流 响应于从存储器单元读出的第二数据的电压。 输出设备耦合到第一节点以输出从存储器单元读出的第一或第二数据。 第一个电流大于第二个电流。
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公开(公告)号：US20120106269A1
公开(公告)日：2012-05-03
申请号：US12913087
申请日：2010-10-27
申请人： Cheng Hung LEE , Jung-Ping YANG
发明人： Cheng Hung LEE , Jung-Ping YANG
IPC分类号： G11C7/12
摘要： The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver.
摘要翻译： 本申请公开了一种具有配置成承载第一数据线信号的第一数据线和被配置为承载第二数据线信号的第二数据线的存储器电路。 此外，第一驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第二数据线信号建立用于第一数据线的第一电流路径。 类似地，第二驱动器耦合到第一数据线和第二数据线，并且被配置为响应于第一数据线信号为第二数据线建立第二电流路径。 存储器电路还具有第一驱动器使能线，其被配置为选择性地使第一驱动器和第二驱动器使能线被配置为选择性地启用第二驱动器。
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