公开(公告)号：US07279416B2

公开(公告)日：2007-10-09

申请号：US10796437

申请日：2004-03-09

申请人： Jung-hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-sook Park

发明人： Jung-hun Seo ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hee-sook Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductive structure is formed in an integrated circuit device by forming a lower conductive pattern on a substrate. A barrier metal layer is formed on the lower conductive pattern. The barrier metal layer is flushed with a gas that includes a halogen group gas and an upper conductive layer is formed on the barrier metal layer.

摘要翻译： 通过在基板上形成下导电图案，在集成电路器件中形成导电结构。 在下导电图案上形成阻挡金属层。 阻挡金属层用包含卤素气体的气体冲洗，并且在阻挡金属层上形成上导电层。

公开(公告)号：US20050179141A1

公开(公告)日：2005-08-18

申请号：US11095006

申请日：2005-03-31

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

公开(公告)号：US07384866B2

公开(公告)日：2008-06-10

申请号：US11095006

申请日：2005-03-31

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L29/40

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

摘要翻译： 半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。 至少一些阻挡金属层被氧化。 在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。 然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

公开(公告)号：US06955983B2

公开(公告)日：2005-10-18

申请号：US10373368

申请日：2003-02-24

申请人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

发明人： Ju-young Yun ,  Gil-heyun Choi ,  Byung-hee Kim ,  Jong-myeong Lee ,  Seung-gil Yang ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/28556 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

摘要： A metal interconnection of a semiconductor device is fabricated by forming a dielectric pattern including a hole therein on a substrate, and forming a barrier metal layer in the hole and on the dielectric layer pattern outside the hole. At least some of the barrier metal layer is oxidized. An anti-nucleation layer is selectively formed on the oxidized barrier metal layer outside the hole that exposes the oxidized barrier metal layer in the hole. A metal layer then is selectively formed on the exposed oxidized barrier layer in the hole.

摘要翻译： 半导体器件的金属互连通过在衬底上形成包括孔的电介质图案，并在孔的外部和电介质层图案上形成阻挡金属层来制造。 至少一些阻挡金属层被氧化。 在孔的氧化阻挡金属层上选择性地形成抗成核层，该氧化的阻挡金属层露出孔中的氧化的阻挡金属层。 然后在孔中的暴露的氧化阻挡层上选择性地形成金属层。

公开(公告)号：US06951814B2

公开(公告)日：2005-10-04

申请号：US10649154

申请日：2003-08-27

申请人： Byung-hee Kim ,  Gil-heyun Choi ,  Ju-young Yun ,  Jung-hun Seo

发明人： Byung-hee Kim ,  Gil-heyun Choi ,  Ju-young Yun ,  Jung-hun Seo

IPC分类号： H01L21/28 ,  B05D5/12 ,  C23C16/00 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/768

CPC分类号： H01L21/28556 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/7684 ,  H01L21/76877

摘要： Methods of forming a metal wiring layer on an integrated circuit include forming an insulating pattern including a recess region on an integrated circuit substrate. A metal layer is formed in the recess region and on a top surface of the insulting pattern. The metal layer is removed from the top surface of the insulating pattern adjacent the recess region and from an upper portion of the recess region. An aluminum film is formed on the metal layer at a process temperature less than a reflow temperature of the metal layer to substantially fill the upper portion of the recess region after removing the metal layer. A metal film is formed on the aluminum film at a process temperature less than the reflow temperature of the etched metal layer.

摘要翻译： 在集成电路上形成金属布线层的方法包括在集成电路基板上形成包括凹部区域的绝缘图案。 在凹陷区域和绝缘图案的顶表面上形成金属层。 金属层从绝缘图案的顶表面与凹陷区域相邻并且从凹陷区域的上部移除。 在金属层上以低于金属层的回流温度的工艺温度形成铝膜，以在去除金属层之后基本上填充凹部区域的上部。 在低于蚀刻金属层的回流温度的工艺温度下，在铝膜上形成金属膜。