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    Method of processing a polysilicon film on a single-crystal silicon substrate
    5.
    发明授权
    Method of processing a polysilicon film on a single-crystal silicon substrate 失效
    在单晶硅衬底上处理多晶硅膜的方法

    公开(公告)号：US5593906A

    公开(公告)日：1997-01-14

    申请号：US489234

    申请日：1995-06-12

    申请人： Junzoh Shimizu

    发明人： Junzoh Shimizu

    IPC分类号： H01L21/302 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L21/306 ,  H01L21/328

    CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/32137 ,  Y10S438/924

    摘要： A method of processing a polysilicon film formed on a single-crystal silicon substrate which can remove the polysilicon film with good selectivity in a fabrication process of semiconductor devices. First, a polysilicon film having an N-portion to be removed is formed on a single-crystal silicon substrate and then, the portion is selectively removed by the reactive ion etching using a Cl.sub.2 gas or mixed gases including a Cl.sub.2 gas. Preferably, N-impurity doping into the polysilicon film is performed by P or As ion-implantation with a dose of 1.times.10.sup.15 cm.sup.-2 or more. A Cl.sub.2 gas, mixed gases of Cl.sub.2 and BCl.sub.3, mixed gases of Cl.sub.2 and HBr, mixed gases of Cl.sub.2 and BBr.sub.3, and mixed gases of Cl.sub.2 and SiCl.sub.4 are preferably used.

    摘要翻译： 一种处理形成在单晶硅衬底上的多晶硅膜的方法，其可以在半导体器件的制造工艺中以良好的选择性去除多晶硅膜。 首先，在单晶硅衬底上形成具有要去除的N部分的多晶硅膜，然后通过使用Cl 2气体的反应离子蚀刻或包括Cl 2气体的混合气体选择性地除去该部分。 优选地，通过P或As离子注入以1×10 15 cm -2以上的剂量进行掺杂到多晶硅膜中的N杂质。 优选使用Cl 2气体，Cl 2和BCl 3的混合气体，Cl 2和HBr的混合气体，Cl 2和BBr 3的混合气体，以及Cl 2和SiCl 4的混合气体。

    Self-aligned process for forming dielectrically isolating regions formed in semiconductor device
    6.
    发明授权
    Self-aligned process for forming dielectrically isolating regions formed in semiconductor device 失效
    用于形成在半导体器件中形成介电隔离区的自对准工艺

    公开(公告)号：US4679306A

    公开(公告)日：1987-07-14

    申请号：US779496

    申请日：1985-09-24

    申请人： Junzoh Shimizu

    发明人： Junzoh Shimizu

    IPC分类号： H01L21/301 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/385

    CPC分类号： H01L21/76205 ,  H01L21/033 ,  H01L21/32134 ,  H01L21/76224

    摘要： A process of fabricating a semiconductor device, wherein a semiconductor substrate of one conductivity type has formed therein layers including a semiconductor layer of the opposite conductivity type, an anti-oxidation mask layer, a doped polysilicon layer, an anti-etch mask layer and a silicon oxide film. Within the substrate are defined isolation areas, from which the silicon oxide film, anti-etch mask layer and doped polysilicon layer are selectively etched away. On the resultant structure is formed an undoped or lightly doped polysilicon layer. Then, the structure is heated to cause atoms of the impurity in the doped polysilicon layer to diffuse into the directly adjacent portions of the undoped or lightly doped polysilicon layer. The undoped or lightly doped polysilicon layer is then etched away over its areas on the silicon oxide film and on the device isolation areas of the substrate. The anti-oxidation mask layer is partially etched away. An exposed portion of the semiconductor layer on the substrate, silicon oxide film, and exposed portions of the undoped or lightly doped polysilicon layer are then etched away. The anti-oxidation mask layer is selectively etched away with the anti-etch mask layer being used as a mask. The residual portions of the anti-oxidation mask layer are then used as a mask to form dielectric regions in the isolation areas of the structure.

    摘要翻译： 一种制造半导体器件的方法，其中形成一种导电类型的半导体衬底，其中包括具有相反导电类型的半导体层的层，抗氧化掩模层，掺杂多晶硅层，抗蚀刻掩模层和 氧化硅膜。 在衬底内是限定的隔离区域，氧化硅膜，抗蚀刻掩模层和掺杂多晶硅层从该隔离区被选择性地蚀刻掉。 在所得结构上形成未掺杂或轻掺杂的多晶硅层。 然后，加热结构以使掺杂多晶硅层中的杂质原子扩散到未掺杂或轻掺杂多晶硅层的直接相邻部分。 然后将未掺杂或轻掺杂的多晶硅层在其氧化硅膜上的区域和衬底的器件隔离区域上蚀刻掉。 抗氧化掩模层被部分蚀刻掉。 然后蚀刻掉衬底上的半导体层的暴露部分，氧化硅膜和未掺杂或轻掺杂的多晶硅层的暴露部分。 用抗蚀刻掩模层作为掩模，选择性地蚀刻掉抗氧化掩模层。 然后将抗氧化掩模层的剩余部分用作掩模，以在结构的隔离区域中形成电介质区域。

    Method of manufacturing bipolar transistor
    7.
    发明授权
    Method of manufacturing bipolar transistor 失效
    制造双极晶体管的方法

    公开(公告)号：US4980305A

    公开(公告)日：1990-12-25

    申请号：US372424

    申请日：1989-06-26

    申请人： Yasuo Kadota ,  Junzoh Shimizu

    发明人： Yasuo Kadota ,  Junzoh Shimizu

    IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/60 ,  H01L21/762 ,  H01L29/06 ,  H01L29/732

    CPC分类号： H01L21/76897 ,  H01L21/28525 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66272 ,  Y10S148/011

    摘要： A bipolar transistor in which a base region and a collector lead-out portion is separated is disclosed. The base region and an active collector portion under the base region is surrounded by a narrow trench filling an insulating film, and the trench is in turn surrounded by the collector lead-out portion. A collector electrode is contacted to the upper surface of the collector lead-out portion such that the collector contact surrounds the active collector portion via the trench, in the plan view.

    摘要翻译： 公开了一种分离基极区域和集电极导出部分的双极晶体管。 底部区域下方的基极区域和有源集电极部分被填充绝缘膜的窄沟槽围绕，并且沟槽又由集电极引出部分包围。 集电极电极在集电极引出部分的上表面接触，使得集电极触点在平面图中经由沟槽围绕有源集电极部分。

    Method of manufacturing bipolar transistor having a reduced parasitic capacitance
    8.
    发明授权
    Method of manufacturing bipolar transistor having a reduced parasitic capacitance 失效
    制造具有减小的寄生电容的双极晶体管的方法

    公开(公告)号：US4980302A

    公开(公告)日：1990-12-25

    申请号：US446364

    申请日：1989-12-05

    申请人： Junzoh Shimizu

    发明人： Junzoh Shimizu

    IPC分类号： H01L29/73 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L21/2257 ,  H01L21/28525 ,  H01L29/0804 ,  H01L29/1004 ,  H01L29/732

    摘要： A bipolar semiconductor device comprises a substrate, a collector region formed of an epitaxial layer of a first conduction type formed on the substrate, a field oxide layer formed on the epitaxial layer so as to define a device formation zone in a device isolation manner, a recess formed in the device formation zone in alignment with an edge of the field oxide layer, a polycrystalline silicon layer of a second conduction type opposite to the first conduction type and formed on a side wall of the recess and on the field oxide layer, and an base region composed of a graft base region and an active base region. The graft base region is formed of a diffused region of the second conduction type formed in the epitaxial layer within the device formation zone by diffusion of impurity from the polycrystalline silicon layer of the second conduction type, and the active base region is formed of a doped region of the second conduction type formed integrally with the polycrystalline silicon layer of the second conduction type under a bottom surface of the recess. The semiconductor device also comprises an insulating layer formed to cover the polycrystalline silicon layer of the second condution type, a polycrystalline silicon layer of the first conduction type formed on at least a bottom of the recess, and an emitter region formed of a diffused region of the first conduction type formed in the diffused region of the second conduction type by diffusion of impurity from the polycrystalline silicon layer of the first conduction type.

    Method of forming an isolation region comprising a trench isolation region and a selective oxidation film involved in a semiconductor device
    9.
    发明授权
    Method of forming an isolation region comprising a trench isolation region and a selective oxidation film involved in a semiconductor device 失效
    形成包括半导体器件中的沟槽隔离区域和选择性氧化膜的隔离区域的方法

    公开(公告)号：US5474953A

    公开(公告)日：1995-12-12

    申请号：US337511

    申请日：1994-11-08

    申请人： Junzoh Shimizu ,  Naoya Matsumoto

    发明人： Junzoh Shimizu ,  Naoya Matsumoto

    IPC分类号： H01L21/76 ,  H01L21/316 ,  H01L21/763

    CPC分类号： H01L21/763 ,  Y10S148/05

    摘要： The present invention provides a novel method of forming an isolation region comprising a trench isolation region and a selective oxidation film region involved in a semiconductor integrated circuit device. A silicon oxide film is deposited on a surface of a trench groove formed within a semiconductor bulk, followed by a deposition of a polycrystalline silicon material. The silicon oxide film within the trench groove is subjected to etching up to a predetermined depth so as to form a hollow portion. A polycrystalline silicon film is deposited within the hollow portion and on both surfaces of the polycrystalline silicon material and the semiconductor bulk. The polycrystalline silicon film within the hollow portion, the polycrystalline silicon material and the semiconductor bulk in the vicinity of the trench groove is subjected to selective oxidation so as to form a selective oxidation film region. It is also permissive that a silicon nitride film is deposited on the silicon oxide film covering the surface of the trench groove prior to the deposition of the polycrystalline silicon material.

    摘要翻译： 本发明提供一种形成隔离区域的新方法，该隔离区域包括半导体集成电路器件中的沟槽隔离区域和选择性氧化膜区域。 在形成于半导体本体内的沟槽的表面上沉积氧化硅膜，然后沉积多晶硅材料。 对沟槽内的氧化硅膜进行刻蚀，直至达到规定的深度，形成中空部。 在多晶硅材料和半导体本体的中空部分和两个表面上沉积多晶硅膜。 中空部分内的多晶硅膜，多晶硅材料和沟槽槽附近的半导体本体进行选择性氧化，形成选择氧化膜区域。 在沉积多晶硅材料之前，氮化硅膜沉积在覆盖沟槽沟槽表面的氧化硅膜上也是允许的。