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公开(公告)号：US20170069643A1
公开(公告)日：2017-03-09
申请号：US15355873
申请日：2016-11-18
IPC分类号： H01L27/115 , H01L29/40 , G11C16/04 , H01L27/02 , G11C16/08 , H01L23/528 , H01L29/06
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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公开(公告)号：US20160268281A1
公开(公告)日：2016-09-15
申请号：US14748882
申请日：2015-06-24
发明人： Hiroyuki KUTSUKAKE
IPC分类号： H01L27/115 , H01L23/528 , G11C16/14 , H01L29/51 , H01L29/792 , H01L29/788 , H01L29/423
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/088 , H01L27/11573 , H01L27/11582 , H01L29/513
摘要： According to one embodiment, a semiconductor memory device includes a substrate; a memory cell unit; a bit line; a first semiconductor area; a second semiconductor area; a first transistor provided on the second semiconductor area and including a first gate electrode, a first gate insulating film, a first electrode, and a second electrode; a second transistor provided on the substrate and including a second gate electrode, a second gate insulating film, a third electrode, and a fourth electrode; and a control unit. The control unit configured to be able to performing an erase operation, the erase operation including: applying a first voltage to the first semiconductor area and the bit line; applying a second voltage being equal to or lower than the first voltage; and applying a third voltage being equal to or lower than the first voltage.
摘要翻译： 根据一个实施例，半导体存储器件包括衬底; 存储单元单元; 有点线 第一半导体区域; 第二半导体区域; 第一晶体管，设置在第二半导体区域上，并且包括第一栅电极，第一栅绝缘膜，第一电极和第二电极; 第二晶体管，设置在所述基板上，并且包括第二栅电极，第二栅绝缘膜，第三电极和第四电极; 和控制单元。 所述控制单元被配置为能够执行擦除操作，所述擦除操作包括：向所述第一半导体区域和所述位线施加第一电压; 施加等于或低于所述第一电压的第二电压; 以及施加等于或低于所述第一电压的第三电压。
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公开(公告)号：US20150262684A1
公开(公告)日：2015-09-17
申请号：US14462831
申请日：2014-08-19
发明人： Hiroyuki KUTSUKAKE
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/0483
摘要： The voltage switching circuit comprises: an nMOS transistor having a gate connected to a first terminal that outputs an output voltage, a drain connected to a power-supply terminal, and a source connected to a second terminal; a first pMOS transistor having a source connected to the second terminal, a drain connected to the first terminal, and a gate provided with a first or second voltage, a source and a well thereof being short-circuited; and a switching circuit connected between a third terminal that supplies the input voltage and the first terminal and configured to turn on when the output voltage is supplied to the first terminal. A gate electrode of the first pMOS transistor is configured by semiconductor including p-type impurity. A concentration of p-type impurity in the gate electrode of the memory cell is different from that of the first pMOS transistor.
摘要翻译： 电压切换电路包括：nMOS晶体管，其具有连接到输出输出电压的第一端子的栅极，连接到电源端子的漏极和连接到第二端子的源极; 具有连接到第二端子的源极的第一pMOS晶体管，连接到第一端子的漏极和设置有第一或第二电压，源极和阱的栅极短路的栅极; 以及连接在提供输入电压的第三端子和第一端子之间并且当输出电压被提供给第一端子时被配置为导通的开关电路。 第一pMOS晶体管的栅电极由包括p型杂质的半导体构成。 存储单元的栅电极中p型杂质的浓度与第一pMOS晶体管的浓度不同。
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公开(公告)号：US20150023111A1
公开(公告)日：2015-01-22
申请号：US14508807
申请日：2014-10-07
发明人： Hiroyuki KUTSUKAKE
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11546
摘要： A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well.
摘要翻译： 实施例的非易失性半导体存储器件包括p型半导体衬底，在半导体衬底中形成的第一P阱，并且其上形成有多个存储单元，围绕第一P阱的第一N阱以及 将第一P阱与半导体衬底电分离，配置为产生第一负电压的第一负电压产生单元，被配置为升高电压并产生升压电压的升压单元，以及连接到第一P阱的第一 负电压产生单元，升压单元和第一P阱，并且被配置为在第一负电压和升压电压之间切换电压，该电压被施加到第一P阱。
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公开(公告)号：US20140117458A1
公开(公告)日：2014-05-01
申请号：US14150366
申请日：2014-01-08
IPC分类号： H01L29/40 , H01L27/112
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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公开(公告)号：US20130264627A1
公开(公告)日：2013-10-10
申请号：US13908435
申请日：2013-06-03
IPC分类号： H01L27/115 , H01L27/105
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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