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公开(公告)号：US20170069643A1
公开(公告)日：2017-03-09
申请号：US15355873
申请日：2016-11-18
IPC分类号： H01L27/115 , H01L29/40 , G11C16/04 , H01L27/02 , G11C16/08 , H01L23/528 , H01L29/06
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
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公开(公告)号：US20170053933A1
公开(公告)日：2017-02-23
申请号：US15344876
申请日：2016-11-07
发明人： Takeshi KAMIGAICHI
IPC分类号： H01L27/115 , H01L29/423 , H01L29/417
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/41741 , H01L29/4234
摘要： According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
摘要翻译： 根据一个实施例，第一部分的半导体本体包括第一半导体部件和第二半导体部件。 第一半导体部件沿堆叠方向延伸。 第二半导体部件设置在第一半导体部件和第一电极层之间，并且具有比第一半导体部件更靠近第一电极层侧的端部。 第二部分的第一绝缘膜包括第一绝缘部分和第二绝缘部分。 第一绝缘部分沿堆叠方向延伸。 第二绝缘部分设置在第一绝缘部分和第二电极层之间，并且具有比第一绝缘部分更靠近第二电极层侧的端部。
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公开(公告)号：US20160268293A1
公开(公告)日：2016-09-15
申请号：US14827495
申请日：2015-08-17
发明人： Takeshi KAMIGAICHI
IPC分类号： H01L27/115 , H01L29/423 , H01L29/417
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/41741 , H01L29/4234
摘要： According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
摘要翻译： 根据一个实施例，第一部分的半导体本体包括第一半导体部件和第二半导体部件。 第一半导体部件沿堆叠方向延伸。 第二半导体部件设置在第一半导体部件和第一电极层之间，并且具有比第一半导体部件更靠近第一电极层侧的端部。 第二部分的第一绝缘膜包括第一绝缘部分和第二绝缘部分。 第一绝缘部分沿堆叠方向延伸。 第二绝缘部分设置在第一绝缘部分和第二电极层之间，并且具有比第一绝缘部分更靠近第二电极层侧的端部。
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公开(公告)号：US20160197035A1
公开(公告)日：2016-07-07
申请号：US14996071
申请日：2016-01-14
IPC分类号： H01L23/528 , H01L23/522
CPC分类号： H01L23/5283 , H01L21/0217 , H01L21/76805 , H01L21/76816 , H01L21/76831 , H01L21/76883 , H01L23/5226 , H01L23/528 , H01L27/0688 , H01L27/101 , H01L27/1021 , H01L27/11556 , H01L27/1157 , H01L27/11578 , H01L27/24 , H01L45/06 , H01L2924/0002 , Y10T156/1057 , H01L2924/00
摘要： A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
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5.发明申请NONVOLATILE SEMICONDUCTOR MEMORY HAVING A WORD LINE BENT TOWARDS A SELECT GATE LINE SIDE 有权具有一个字线的非线性半导体存储器选择门电路公开(公告)号：US20140293694A1
公开(公告)日：2014-10-02
申请号：US14301102
申请日：2014-06-10
CPC分类号： H01L27/11519 , G11C5/06 , G11C5/063 , G11C16/04 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
摘要翻译： 非易失性半导体存储器包括具有选择栅极晶体管和串联连接的存储单元的单元单元，连接到选择栅极晶体管的选择栅极线和连接到存储单元的字线。 字线的一端弯曲到选择栅线侧，并且边缘连接在字线的弯曲点和远端之间。
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公开(公告)号：US20160268304A1
公开(公告)日：2016-09-15
申请号：US15067830
申请日：2016-03-11
发明人： Keiji IKEDA , Masumi SAITOH , Hideaki AOCHI , Takeshi KAMIGAICHI , Jun FUJIKI
IPC分类号： H01L27/115 , H01L29/24 , H01L29/423 , H01L29/04 , H01L49/02 , H01L23/528 , H01L29/16
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573
摘要： This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.
摘要翻译： 该非易失性半导体存储器件包括：包括存储单元的存储单元阵列; 以及将存储单元阵列连接到外部电路的布线部分。 存储单元阵列包括连接到存储单元并沿层叠方向布置的多个第一导电层。 另一方面，布线部分包括：沿层叠方向布置并分别连接到多个第一导电层的多个第二导电层，多个第二导电层的端部的位置在第一方向交叉处不同 堆叠方向; 从所述第二导电层沿层叠方向延伸的第三导电层; 连接到所述第三导电层的一端的沟道半导体层; 以及通过栅极绝缘膜设置在沟道半导体层的表面上的栅电极布线。
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公开(公告)号：US20160071871A1
公开(公告)日：2016-03-10
申请号：US14633405
申请日：2015-02-27
发明人： Takeshi KAMIGAICHI
IPC分类号： H01L27/115 , H01L21/02 , H01L21/28 , H01L29/45 , H01L29/49
CPC分类号： H01L27/11582 , H01L21/28282 , H01L29/45 , H01L29/495 , H01L29/7827 , H01L29/7926
摘要： According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of inter-layer insulating layers each provided between the plurality of electrode layers; and a columnar portion penetrating the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; and a charge storage film provided between the channel body and each of the electrode layers. Each of the electrode layers includes an edge portion provided closer on a central axis side of the columnar portion than the inter-layer insulating layers. The charge storage film covers the edge portion of each of the electrode layers and separated from each other in the stacking direction.
摘要翻译： 根据一个实施例，半导体存储器件包括层叠体，其包括多个电极层和多个层间绝缘层，每个层间绝缘层设置在多个电极层之间; 以及穿过层叠体并沿层叠体的层叠方向延伸的柱状部。 柱状部分包括沿堆叠方向延伸的通道体; 以及设置在通道体和每个电极层之间的电荷存储膜。 每个电极层包括比层间绝缘层更靠近柱状部分的中心轴侧的边缘部分。 电荷存储膜覆盖每个电极层的边缘部分并且在层叠方向上彼此分离。
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公开(公告)号：US20150262658A1
公开(公告)日：2015-09-17
申请号：US14466022
申请日：2014-08-22
发明人： Takeshi KAMIGAICHI
CPC分类号： G11C11/5635 , G11C5/06 , G11C11/5628 , G11C16/0483
摘要： A semiconductor memory device according to an embodiment comprises: a plurality of memory cells; a word line; a plurality of first bit lines and a plurality of second bit lines; and a control circuit. The control circuit is capable of executing: a determining operation that determines whether the memory cell which is to be a write-target includes an erase-target cell whose threshold voltage is to be the erase state, or not; and an inverting operation that inverts selection or unselection of the bit line connected to one of the two memory cells adjacent to the erase-target cell, in the first write operation and the second write operation.
摘要翻译： 根据实施例的半导体存储器件包括：多个存储单元; 字线 多个第一位线和多个第二位线; 和控制电路。 控制电路能够执行：确定操作，其确定作为写入目标的存储单元是否包括其阈值电压将为擦除状态的擦除目标单元; 以及在第一写入操作和第二写入操作中反转连接到与擦除目标单元相邻的两个存储单元之一的位线的选择或不选择的反相操作。
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公开(公告)号：US20170278862A1
公开(公告)日：2017-09-28
申请号：US15266416
申请日：2016-09-15
发明人： Jun FUJIKI , Takeshi KAMIGAICHI , Hideaki AOCHI
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： A semiconductor memory device according to an embodiment comprises: a plurality of memory strings arranged in a first direction intersecting a surface of a semiconductor substrate, each of the memory strings including a plurality of memory transistors connected in series in a second direction along the surface of the semiconductor substrate; a source side select transistor connected to one end of the memory string; a drain side select transistor connected to the other end of the memory string; a plurality of source lines respectively connected, via the source side select transistor, to each of the plurality of memory strings arranged along the first direction; a bit line commonly connected, via the drain side select transistor, to the plurality of memory strings arranged along the first direction; a word line connected to a gate electrode of the memory transistor; and a layer selector disposed between the source line and the source side select transistor and commonly connected to the plurality of memory strings arranged along the first direction.
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公开(公告)号：US20160268295A1
公开(公告)日：2016-09-15
申请号：US14828621
申请日：2015-08-18
发明人： Takeshi KAMIGAICHI
IPC分类号： H01L27/115 , H01L29/167
CPC分类号： H01L27/11582 , H01L27/1157
摘要： According to one embodiment, a semiconductor device includes a stacked body and a columnar portion. The stacked body includes a plurality of electrode layers stacked with an insulator between the electrode layers. The columnar portion includes a semiconductor body extending in the stacked body in a stacking direction of the stacked body, and a charge storage film provided between the semiconductor body and the electrode layers. The columnar portion includes a first portion with a first diameter, and a second portion with a second diameter smaller than the first diameter. The first portion has a higher concentration of an impurity than a concentration of the impurity of the second portion. The impurity contains at least one of boron, arsenic, and phosphorus.
摘要翻译： 根据一个实施例，半导体器件包括堆叠体和柱状部分。 堆叠体包括在电极层之间堆叠有绝缘体的多个电极层。 柱状部分包括在层叠体的堆叠方向上沿堆叠体延伸的半导体本体，以及设置在半导体主体和电极层之间的电荷存储膜。 柱状部分包括具有第一直径的第一部分和具有小于第一直径的第二直径的第二部分。 第一部分具有比第二部分的杂质浓度更高的杂质浓度。 杂质含有硼，砷和磷中的至少一种。
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