-
公开(公告)号：US09590052B2
公开(公告)日：2017-03-07
申请号：US14150366
申请日：2014-01-08
IPC分类号： H01L29/40 , H01L27/115 , H01L27/105 , H01L27/112
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
-
公开(公告)号：US09202559B2
公开(公告)日：2015-12-01
申请号：US14466022
申请日：2014-08-22
发明人： Takeshi Kamigaichi
CPC分类号： G11C11/5635 , G11C5/06 , G11C11/5628 , G11C16/0483
摘要： A semiconductor memory device according to an embodiment comprises: a plurality of memory cells; a word line; a plurality of first bit lines and a plurality of second bit lines; and a control circuit. The control circuit is capable of executing: a determining operation that determines whether the memory cell which is to be a write-target includes an erase-target cell whose threshold voltage is to be the erase state, or not; and an inverting operation that inverts selection or unselection of the bit line connected to one of the two memory cells adjacent to the erase-target cell, in the first write operation and the second write operation.
摘要翻译： 根据实施例的半导体存储器件包括：多个存储单元; 字线 多个第一位线和多个第二位线; 和控制电路。 控制电路能够执行：确定操作，其确定作为写入目标的存储单元是否包括其阈值电压将为擦除状态的擦除目标单元; 以及在第一写入操作和第二写入操作中反转连接到与擦除目标单元相邻的两个存储单元之一的位线的选择或不选择的反相操作。
-
公开(公告)号：US20150263121A1
公开(公告)日：2015-09-17
申请号：US14483601
申请日：2014-09-11
发明人： Kana HIRAYAMA , Ryuji Ohba , Takeshi Kamigaichi
IPC分类号： H01L29/51 , H01L29/423 , H01L21/28 , H01L29/66 , H01L21/762 , H01L27/115 , H01L29/788 , H01L29/49
CPC分类号： H01L27/11519 , H01L21/76224 , H01L27/11521 , H01L29/40114 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A semiconductor device including semiconductor substrate having an active region and an element isolation region, the active region isolated by the element isolation region, the element isolation region provided with an element isolation trench; a memory-cell transistor formed above the semiconductor substrate and having a gate electrode formed above the active region via a first insulating film, the gate electrode formed of a stack including a floating gate electrode, a first interelectrode insulating film, and a control gate electrode; an element isolation insulating film filled in the element isolation trench; and a second interelectrode insulating film disposed above the element isolation insulating film so as to form a stack of the second interelectrode insulating film and the control electrode above the element isolation insulating and a dielectric constant of the second interelectrode insulating film being higher than a dielectric constant of the first interelectrode insulating film.
摘要翻译： 一种半导体器件，包括具有有源区和元件隔离区的半导体衬底，所述有源区由元件隔离区隔离，元件隔离区设置有元件隔离沟槽; 形成在所述半导体衬底上并且具有通过第一绝缘膜形成在所述有源区上方的栅电极的存储单元晶体管，所述栅电极由包括浮置栅电极，第一电极间绝缘膜和控制栅电极 ; 填充在元件隔离沟槽中的元件隔离绝缘膜; 以及第二电极间绝缘膜，其设置在所述元件隔离绝缘膜的上方，以在所述元件隔离绝缘件的上方形成所述第二电极间绝缘膜和所述控制电极的叠层，并且所述第二电极间绝缘膜的介电常数高于介电常数 的第一电极间绝缘膜。
-
公开(公告)号：US09059300B2
公开(公告)日：2015-06-16
申请号：US13837552
申请日：2013-03-15
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/11548 , H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529 , H01L29/788
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
-
公开(公告)号：US08698274B2
公开(公告)日：2014-04-15
申请号：US13908435
申请日：2013-06-03
IPC分类号： H01L21/76
CPC分类号： H01L27/11526 , G11C16/0408 , G11C16/08 , H01L23/528 , H01L27/0207 , H01L27/105 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/0649 , H01L29/402 , H01L29/404
摘要： A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.
摘要翻译： 半导体器件包括在半导体衬底的主表面上以矩阵形式布置的多个高电压绝缘栅场效应晶体管，每个具有栅电极，形成在栅电极上的栅电极接触和布线 形成在栅极电极上的层在栅极宽度方向上相邻地接触以电连接沿栅极宽度方向布置的栅电极。 并且该器件包括设置在位于栅极宽度方向和栅极长度方向相邻的晶体管之间的元件隔离区域的部分上的屏蔽栅极，用于施加与施加到栅极宽度方向上的电位的极性不同的参考电位或电位 晶体管的栅极，以将晶体管的电流路径导通到元件隔离区域。
-
公开(公告)号：US20130294164A1
公开(公告)日：2013-11-07
申请号：US13935637
申请日：2013-07-05
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , G11C5/06 , G11C5/063 , G11C16/04 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
-
公开(公告)号：US20170200734A1
公开(公告)日：2017-07-13
申请号：US15228378
申请日：2016-08-04
发明人： Jun Fujiki , Takeshi Kamigaichi , Hideaki Aochi
IPC分类号： H01L27/115 , H01L29/04 , H01L21/02 , H01L29/417 , H01L23/532 , H01L21/28 , H01L29/16 , H01L29/45
CPC分类号： H01L27/11582 , H01L21/02532 , H01L21/02592 , H01L21/28273 , H01L21/28282 , H01L23/53204 , H01L27/11519 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/04 , H01L29/16 , H01L29/41741 , H01L29/456
摘要： One embodiment includes a plurality of memory cells and a plurality of conducting layers. The memory cells are three-dimensionally disposed on a semiconductor substrate. The conducting layers are disposed in a laminating direction. Each of the plurality of the conducting layers is connected to each of the plurality of the memory cells. Each conducting layer has a structure where a first conductive film and a second conductive film are laminated in the laminating direction. The conducting layers adjacent to one another in the laminating direction have a laminating order of the first conductive film and the second conductive film different from one another.
-
公开(公告)号：US09202816B2
公开(公告)日：2015-12-01
申请号：US14626566
申请日：2015-02-19
IPC分类号： H01L27/115 , G11C16/04 , G11C5/06
CPC分类号： H01L27/11519 , G11C5/06 , G11C5/063 , G11C16/04 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
-
9.发明授权Nonvolatile semiconductor memory having a word line bent towards a select gate line side 有权具有向选择栅线侧弯曲的字线的非易失性半导体存储器公开(公告)号：US08786096B2
公开(公告)日：2014-07-22
申请号：US13935637
申请日：2013-07-05
IPC分类号： H01L29/41 , H01L27/115
CPC分类号： H01L27/11519 , G11C5/06 , G11C5/063 , G11C16/04 , G11C16/0483 , H01L27/115 , H01L27/11524
摘要： A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.
摘要翻译： 非易失性半导体存储器包括具有选择栅极晶体管和串联连接的存储单元的单元单元，连接到选择栅极晶体管的选择栅极线和连接到存储单元的字线。 字线的一端弯曲到选择栅线侧，并且边缘连接在字线的弯曲点和远端之间。
-
公开(公告)号：US09524982B2
公开(公告)日：2016-12-20
申请号：US14827495
申请日：2015-08-17
发明人： Takeshi Kamigaichi
IPC分类号： H01L27/115 , H01L29/417 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/1157 , H01L29/41741 , H01L29/4234
摘要： According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
摘要翻译： 根据一个实施例，第一部分的半导体本体包括第一半导体部件和第二半导体部件。 第一半导体部件沿堆叠方向延伸。 第二半导体部件设置在第一半导体部件和第一电极层之间，并且具有比第一半导体部件更靠近第一电极层侧的端部。 第二部分的第一绝缘膜包括第一绝缘部分和第二绝缘部分。 第一绝缘部分沿堆叠方向延伸。 第二绝缘部分设置在第一绝缘部分和第二电极层之间，并且具有比第一绝缘部分更靠近第二电极层侧的端部。
-
-
-
-
-
-
-
-
-
搜索结果
20 条记录 (耗时 0.025 秒)
