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1.发明公开公开(公告)号：US20230197167A1
公开(公告)日：2023-06-22
申请号：US18173211
申请日：2023-02-23
Applicant: KIOXIA CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
CPC classification number: G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C16/349 , G11C16/08 , G11C16/10 , G11C16/14
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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公开(公告)号：US20220262439A1
公开(公告)日：2022-08-18
申请号：US17734359
申请日：2022-05-02
Applicant: KIOXIA CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI
Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
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Patent Agency Ranking
公开(公告)号：US20240153560A1
公开(公告)日：2024-05-09
申请号：US18414524
申请日：2024-01-17
Applicant: KIOXIA CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI
CPC classification number: G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3463 , G11C2211/5621
Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
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4.发明申请公开(公告)号：US20220065702A1
公开(公告)日：2022-03-03
申请号：US17189140
申请日：2021-03-01
Applicant: KIOXIA CORPORATION
Inventor： Keisuke TERADA , Eietsu TAKAHASHI
Abstract: A semiconductor storage device includes a memory cell and a control circuit configured to, upon receipt of a command, acquire a first temperature measured by a temperature sensor, and perform an operation corresponding to the command using a parameter corrected based on temperature. When the first temperature is within a predetermined range with respect to a second temperature measured before the command is received, the parameter is corrected using the second temperature. When the first temperature is outside the predetermined range, the parameter is corrected using the first temperature.
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5.发明公开公开(公告)号：US20240347113A1
公开(公告)日：2024-10-17
申请号：US18752870
申请日：2024-06-25
Applicant: KIOXIA CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
CPC classification number: G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/3427 , G11C16/349
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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公开(公告)号：US20240105272A1
公开(公告)日：2024-03-28
申请号：US18460262
申请日：2023-09-01
Applicant: Kioxia Corporation
Inventor： Eietsu TAKAHASHI
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/26
Abstract: A semiconductor memory device includes: a first bit line connected to a first string including memory cell transistors; a second bit line connected to a second string including memory cell transistors; a source line connected to the first string and the second string; a word line connected to gates of the memory cell transistors in same rows of the first and strings; a voltage generation circuit configured to apply a first voltage to the first bit line according to a first target level, apply a second voltage to the second bit line according to a second target level, and apply a third voltage to the source line; and a row decoder configured to apply a fourth voltage to the word line to which a first memory cell transistor of the first string and a second memory cell transistor of the second string are connected during a verification operation.
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7.发明公开公开(公告)号：US20240005999A1
公开(公告)日：2024-01-04
申请号：US18467793
申请日：2023-09-15
Applicant: KIOXIA CORPORATION
Inventor： Yasuhiro SHIINO , Eietsu TAKAHASHI , Koki UENO
CPC classification number: G11C16/26 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C16/349 , G11C16/08 , G11C16/10 , G11C16/14
Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.
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