公开(公告)号：US20240212757A1

公开(公告)日：2024-06-27

申请号：US18596753

申请日：2024-03-06

Applicant: KIOXIA CORPORATION

Inventor： Makoto IWAI ,  Hiroshi NAKAMURA

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

公开(公告)号：US20230296669A1

公开(公告)日：2023-09-21

申请号：US17898102

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Takuya KUSAKA ,  Hirosuke NARAI ,  Kazunori MASUDA ,  Makoto IWAI

IPC: G01R31/28 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: G01R31/2896 ,  G01R31/2853 ,  G01R31/2884 ,  H01L24/48 ,  H01L25/0657 ,  H01L23/5386 ,  H01L2224/48147 ,  H01L2224/48149 ,  H01L2224/48229 ,  H01L2924/1438 ,  H01L2924/1431 ,  H01L23/49816

Abstract: A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.

公开(公告)号：US20220084566A1

公开(公告)日：2022-03-17

申请号：US17171025

申请日：2021-02-09

Applicant: Kioxia Corporation

Inventor： Makoto IWAI

IPC: G11C7/10 ,  G11C7/04

Abstract: A semiconductor storage device of embodiments is a semiconductor storage device including a memory cell array including a plurality of non-volatile memory cells, a sequencer configured to control a sequence based on read operation of reading data from the memory cell array, and a column decoder, the sequencer controlling the sequence of changing a ready/busy signal from ready to busy after receiving a read command and an address signal, reading data from the memory cell array using a sense amplifier after changing the ready/busy signal to the busy, changing the ready/busy signal from the busy to the ready after storing data in the data latch circuit, receiving a data output command after changing the ready/busy signal to the ready, and, in a case where a first condition occurs, writing log data including the data stored in the data latch circuit in a memory area of the memory cell array.