公开(公告)号：US20210118862A1

公开(公告)日：2021-04-22

申请号：US17012111

申请日：2020-09-04

申请人： Kioxia Corporation

发明人： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC分类号： H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00

摘要： A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US20230317173A1

公开(公告)日：2023-10-05

申请号：US18326587

申请日：2023-05-31

申请人： Kioxia Corporation

发明人： Masanobu SHIRAKAWA ,  Takuya FUTATSUYAMA ,  Kenichi ABE ,  Hiroshi NAKAMURA ,  Keisuke YONEHAMA ,  Atsuhiro SATO ,  Hiroshi SHINOHARA ,  Yasuyuki BABA ,  Toshifumi MINAMI

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C11/56 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C11/5635 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/3445

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US20220148657A1

公开(公告)日：2022-05-12

申请号：US17585370

申请日：2022-01-26

申请人： KIOXIA CORPORATION

发明人： Masanobu SHIRAKAWA ,  Takuya FUTATSUYAMA ,  Kenichi ABE ,  Hiroshi NAKAMURA ,  Keisuke YONEHAMA ,  Atsuhiro SATO ,  Hiroshi SHINOHARA ,  Yasuyuki BABA ,  Toshifumi MINAMI

IPC分类号： G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42

摘要： A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US20240212757A1

公开(公告)日：2024-06-27

申请号：US18596753

申请日：2024-03-06

申请人： KIOXIA CORPORATION

发明人： Makoto IWAI ,  Hiroshi NAKAMURA

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/0483 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459

摘要： A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

公开(公告)号：US20230307434A1

公开(公告)日：2023-09-28

申请号：US18203952

申请日：2023-05-31

申请人： Kioxia Corporation

发明人： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC分类号： H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2924/14511 ,  H01L2224/08145 ,  H01L2924/1431

摘要： A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.