公开(公告)号：US11600772B2

公开(公告)日：2023-03-07

申请号：US17014587

申请日：2020-09-08

Applicant: Kioxia Corporation

Inventor： Hiroki Kawai ,  Katsuyoshi Komatsu ,  Tadaomi Daibou ,  Hiroki Tokuhira ,  Masatoshi Yoshikawa ,  Yuichi Ito

IPC: H01L45/00

Abstract: A resistance variable device of an embodiment includes a stack arranged between a first electrode and a second electrode and including a resistance variable layer and a chalcogen-containing layer. The chalcogen-containing layer contains a material having a composition represented by a general formula: C1xC2yAz, where C1 is at least one element selected from Sc, Y, Zr, and Hf, C2 is at least one element selected from C, Si, Ge, B, Al, Ga, and In, A is at least one element selected from S, Se, and Te, and x, y, and z are numbers representing atomic ratios satisfying 0

公开(公告)号：US12033718B2

公开(公告)日：2024-07-09

申请号：US17944725

申请日：2022-09-14

Applicant: Kioxia Corporation

Inventor： Kensuke Ota ,  Marina Yamaguchi ,  Masatoshi Yoshikawa

IPC: G11C7/10 ,  G06N20/00 ,  G11C7/14

CPC classification number: G11C7/1096 ,  G06N20/00 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/14

Abstract: A semiconductor device according to an embodiment includes first to fifth interconnects, first to third memory cells, and a control circuit. The control circuit is configured to execute machine learning. Each of the first memory cells, the second memory cells, and the third memory cells includes a resistance changing element. In the machine learning, the control circuit is configured to: execute a write operation using a common write voltage to each of the second memory cells; and after the write operation, input input data to each of the first interconnects, and change a resistance value of at least one third memory cell of the third memory cells based on the input data and a signal output from each of the fifth interconnects based on the input data.

公开(公告)号：US12243572B2

公开(公告)日：2025-03-04

申请号：US18178993

申请日：2023-03-06

Applicant: Kioxia Corporation

Inventor： Masatoshi Yoshikawa

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85

Abstract: A magnetic memory device includes first to third conductors and a 3-terminal type memory cell coupled to the first to third conductors. The memory cell includes: a fourth conductor and a magnetoresistance effect element provided between the fourth and third conductors. The magnetoresistance effect element includes: a first ferromagnet in contact with the fourth conductor; a second ferromagnet provided in an opposite side of the fourth conductor with respect to the first ferromagnet; a dielectric between the first and second ferromagnets; a third ferromagnet provided in an opposite side of the first ferromagnet with respect to the second ferromagnet; and a nonmagnet provided between the second and third ferromagnets. A concentration of a noble metal contained in the first ferromagnet is higher than a concentration of the noble metal contained in the second ferromagnet.

公开(公告)号：US12170106B2

公开(公告)日：2024-12-17

申请号：US17682667

申请日：2022-02-28

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Asao ,  Masatoshi Yoshikawa

IPC: G11C11/16 ,  G11C5/08 ,  H10B61/00 ,  H10N50/10

Abstract: According to one embodiment, a magnetic memory device includes first to third conductor layers, and a three-terminal-type memory cell connected to the first to third conductor layers. The first memory cell includes a fourth conductor layer, a magnetoresistance effect element, a two-terminal-type first switching element, and a two-terminal-type second switching element. The fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion which is connected to the third conductor layer. The magnetoresistance effect element is connected between the third conductor layer and the fourth conductor layer. The first switching element is connected between the second conductor layer and the fourth conductor layer. The second switching element is connected between the first conductor layer and the third conductor layer.

公开(公告)号：US12144267B2

公开(公告)日：2024-11-12

申请号：US17460898

申请日：2021-08-30

Applicant: Kioxia Corporation

Inventor： Jieqiong Zhang ,  Masatoshi Yoshikawa ,  Tadaomi Daibou

IPC: H10B63/00 ,  H10N70/00

Abstract: According to one embodiment, a selector device includes a first electrode, a second electrode, and a selector layer disposed between the first electrode and the second electrode. At least one of the first electrode or the second electrode includes a stacked film. The stacked film includes a first layer including a first material with a first Debye temperature, and a second layer in contact with the first layer and including a second material with a second Debye temperature lower than the first Debye temperature. A ratio of the first Debye temperature to the second Debye temperature is equal to or greater than 5.

公开(公告)号：US11322189B2

公开(公告)日：2022-05-03

申请号：US16904080

申请日：2020-06-17

Applicant: Kioxia Corporation

Inventor： Masatoshi Yoshikawa

IPC: H01L43/10 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, wherein the first magnetic layer includes a first sub-magnetic layer, a second sub-magnetic layer, and a first intermediate layer between the first sub-magnetic layer and the second sub-magnetic layer, and the first sub-magnetic layer is provided between the nonmagnetic layer and the second sub-magnetic layer and has a magnetization direction antiparallel to a magnetization direction of the second sub-magnetic layer and has a magnetization amount smaller than that of the second sub-magnetic layer.