公开(公告)号：US12069872B2

公开(公告)日：2024-08-20

申请号：US18231304

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US11985834B2

公开(公告)日：2024-05-14

申请号：US17346478

申请日：2021-06-14

Applicant: Kioxia Corporation

Inventor： Yoshiki Kamata ,  Misako Morota ,  Yukihiro Nomura ,  Yoshiaki Asao

IPC: H10B63/00 ,  H10B53/20 ,  H10B53/30

CPC classification number: H10B63/845 ,  H10B53/20 ,  H10B53/30 ,  H10B63/34

Abstract: A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.

公开(公告)号：US11948636B2

公开(公告)日：2024-04-02

申请号：US17693935

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Yoshiki Kamata ,  Yoshiaki Asao ,  Yukihiro Nomura ,  Misako Morota ,  Daisaburo Takashima ,  Takahiko Iizuka ,  Shigeru Kawanaka

IPC: G11C13/00 ,  G11C5/06 ,  H10B63/00 ,  H10N70/00

CPC classification number: G11C13/0069 ,  G11C5/06 ,  H10B63/30 ,  H10N70/826 ,  G11C2013/0078 ,  G11C2213/75

Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.

公开(公告)号：US11756617B2

公开(公告)日：2023-09-12

申请号：US17961433

申请日：2022-10-06

Applicant: Kioxia Corporation

Inventor： Yoshiaki Asao

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H10N70/20

CPC classification number: G11C13/0069 ,  G11C11/161 ,  G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0064 ,  H10N70/20 ,  G11C2213/79

Abstract: A variable resistance memory device includes plural first, second, and third conductors, plural memory cells, and a write circuit. Each memory cell is between one first conductor and one third conductor, and includes a first sub memory cell and a second sub memory cell. The first sub memory cell is between the one first conductor and one second conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is between the one second conductor and the one third conductor, and includes a second variable resistance element and a second bidirectional switching element. The write circuit applies a first potential to the first and third conductors of a selected memory cell, a second potential to the second conductor of the selected memory cell, and a third potential to the first and third conductors of non-selected memory cells.

公开(公告)号：US12236990B2

公开(公告)日：2025-02-25

申请号：US18184682

申请日：2023-03-16

Applicant: Kioxia Corporation

Inventor： Hideyuki Sugiyama ,  Kenji Fukuda ,  Yoshiaki Asao ,  Kazumasa Sunouchi

IPC: G11C11/00 ,  G11C11/16

Abstract: According to one embodiment, a magnetic memory device includes a first wiring line, a plurality of second wiring lines, a plurality of first memory cells each including a first magnetoresistance effect element and a first selector connected in series, and a first switch. A respective one of the first memory cells is connected between the first wiring line and a respective one of the second wiring lines, a first voltage is applied to the second wiring line connected to a selected first memory cell, and a second voltage is applied to the second wiring line connected to a non-selected first memory cell, a first terminal of the first switch is connected to the first wiring line, and a third voltage is applied to a second terminal of the first switch.

公开(公告)号：US12219889B2

公开(公告)日：2025-02-04

申请号：US17679948

申请日：2022-02-24

Applicant: KIOXIA CORPORATION

Inventor： Masahiro Takahashi ,  Yoshiaki Asao ,  Yukihiro Nomura ,  Daisaburo Takashima

IPC: H10N70/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

Abstract: A semiconductor storage device includes a memory cell including a core portion that extends in a first direction above a semiconductor substrate; a variable resistance layer that extends in the first direction and is in contact with the core portion; a semiconductor layer that extends in the first direction and is in contact with the variable resistance layer; a first insulator layer that extends in the first direction and is in contact with the semiconductor layer; and a first voltage applying electrode that extends in a second direction orthogonal to the first direction and is in contact with the first insulator layer. The core portion is a vacuum region, or a region containing inert gas.

公开(公告)号：US11765916B2

公开(公告)日：2023-09-19

申请号：US17348839

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Takahiko Iizuka ,  Daisaburo Takashima ,  Ryu Ogiwara ,  Rieko Funatsuki ,  Yoshiki Kamata ,  Misako Morota ,  Yoshiaki Asao ,  Yukihiro Nomura

IPC: G11C11/00 ,  H10B63/00 ,  G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  G11C13/003 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/066 ,  H10N70/231 ,  H10N70/8828 ,  G11C2213/75

Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.

公开(公告)号：US11495295B2

公开(公告)日：2022-11-08

申请号：US17349162

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Yoshiaki Asao

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/16 ,  H01L45/00

Abstract: A variable resistance memory device includes: a memory cell including a first and second sub memory cell; and a first, second and third conductor. The first sub memory cell is above the first conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is above the second conductor, and includes a second variable resistance element and a second bidirectional switching element. The second conductor is above the first sub memory cell. The third conductor is above the second sub memory cell. The variable resistance memory device is configured to receive first data and to write the first data to the memory cell when the first data does not match second data read from the memory cell.

公开(公告)号：US12170106B2

公开(公告)日：2024-12-17

申请号：US17682667

申请日：2022-02-28

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Asao ,  Masatoshi Yoshikawa

IPC: G11C11/16 ,  G11C5/08 ,  H10B61/00 ,  H10N50/10

Abstract: According to one embodiment, a magnetic memory device includes first to third conductor layers, and a three-terminal-type memory cell connected to the first to third conductor layers. The first memory cell includes a fourth conductor layer, a magnetoresistance effect element, a two-terminal-type first switching element, and a two-terminal-type second switching element. The fourth conductor layer includes a first portion connected to the first conductor layer, a second portion connected to the second conductor layer, and a third portion which is connected to the third conductor layer. The magnetoresistance effect element is connected between the third conductor layer and the fourth conductor layer. The first switching element is connected between the second conductor layer and the fourth conductor layer. The second switching element is connected between the first conductor layer and the third conductor layer.