公开(公告)号：US20220301643A1

公开(公告)日：2022-09-22

申请号：US17459441

申请日：2021-08-27

Applicant: KIOXIA CORPORATION

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Reiko SUMI ,  Reika TANAKA ,  Masumi SAITOH

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/08

Abstract: A semiconductor storage device includes a memory cell array including a plurality of memory strings, each connected between one of a plurality of bit lines and a source line and includes a first select transistor, a second select transistor, and memory cell transistors that are connected in series between the first select transistor and the second select transistor, and a plurality of word lines respectively connected to gates of the memory cell transistors in each memory string. A threshold voltage of the memory cell transistor is increased when a voltage that is applied to the word line connected to the gate thereof is lower than a voltage of a channel thereof. In the erase operation, data stored in the memory cell transistors connected to a selected one of the word lines are erased while data stored in the memory cell transistors not connected to the selected word line are not erased.

公开(公告)号：US20240324169A1

公开(公告)日：2024-09-26

申请号：US18601832

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Reiko SUMI ,  Takashi INUKAI ,  Tsuneo INABA ,  Takayuki MIYAZAKI

IPC: H10B12/00 ,  H01L23/482 ,  H01L23/538

CPC classification number: H10B12/0335 ,  H01L23/4824 ,  H01L23/538 ,  H10B12/485 ,  H10B12/488

Abstract: According to one embodiment, a memory device includes, a memory cell array including first to fourth sub-arrays, a first bit line coupled to the first sub-array and the second sub-array, a second bit line arranged side by side with the first bit line in a first direction and coupled to the third sub-array and the fourth sub-array, a third bit line arranged at a position different from the first bit line in a second direction and coupled to at least the second sub-array and the third sub-array, a fourth bit line arranged side by side with the third bit line in the first direction and coupled to the fourth sub-array, a first circuit electrically coupled to the first bit line and the second bit line, and a second circuit electrically coupled to the third bit line and the fourth bit line.

公开(公告)号：US20230197177A1

公开(公告)日：2023-06-22

申请号：US17816836

申请日：2022-08-02

Applicant: Kioxia Corporation

Inventor： Kazutaka IKEGAMI ,  Takashi MAEDA ,  Reiko SUMI

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3481 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory system according to an embodiment includes a first bit line, a source line, a first word line, a second word line, a first memory pillar and a control circuit. The control circuit performs a first verify operation to first and second memory cells, a second verify operation to the first memory cell, a third verify operation to the second memory cell and a write operation or a read operation with a lower voltage in accordance with a request from an external device.

公开(公告)号：US20230410913A1

公开(公告)日：2023-12-21

申请号：US18068605

申请日：2022-12-20

Applicant: KIOXIA CORPORATION

Inventor： Reiko SUMI ,  Kazutaka IKEGAMI

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459

Abstract: A semiconductor memory device comprises: a semiconductor layer extending in a first direction; a first and second conductive layer facing the semiconductor layer from one side and the other side in a second direction; and a charge storage layer comprising portions provided between the semiconductor layer and first conductive layer and between the semiconductor layer and second conductive layer. The semiconductor memory device is configured to execute erase operation, first write operation, and second write operation. In the first write operation, the first and second conductive layers are applied with first program voltage. In the second write operation, the first conductive layer is applied with second program voltage, and second conductive layer is applied with second voltage lower than the second program voltage. The second write operation is executed after execution of the erase operation and before execution of the first write operation.

公开(公告)号：US20230078441A1

公开(公告)日：2023-03-16

申请号：US17689182

申请日：2022-03-08

Applicant: Kioxia Corporation

Inventor： Reiko SUMI ,  Takashi MAEDA ,  Hidehiro SHIGA

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: A semiconductor memory device of embodiments includes that in a write operation, the driver applies a first voltage to the first select gate line, applies a second voltage lower than the first voltage to the second select gate line, applies a third voltage equal to or higher than the first voltage to the first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to the second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to the first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to the second dummy word line on a lowermost layer.