公开(公告)号：US20240090222A1

公开(公告)日：2024-03-14

申请号：US18460303

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Tatsufumi HAMADA ,  Yosuke MITSUNO ,  Tomohiro KUKI ,  Yusuke MORIKAWA ,  Ryouji MASUDA ,  Hiroyasu SATO

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A semiconductor memory device includes a stacked body in which a first insulating layer and a first conductive layer are alternately stacked in a first direction. A columnar body includes a first insulating portion extending in the first direction in the stacked body, a first semiconductor portion provided between the first insulating portion and the stacked body, and a third insulating portion provided between a second insulating portion provided between the first semiconductor portion and the stacked body, and the second insulating portion and the stacked body, and has a first end and a second end opposite to the first end. A second conductive layer is provided on the stacked body and is electrically connected to the first semiconductor portion at the first end of the columnar body. The first insulating portion blocks an inner side of the first semiconductor portion at the first end of the columnar body and has a space in the first semiconductor portion at a position closer to the second end than the first end.

公开(公告)号：US20220302138A1

公开(公告)日：2022-09-22

申请号：US17464173

申请日：2021-09-01

Applicant: Kioxia Corporation

Inventor： Yosuke MITSUNO ,  Tatsufumi HAMADA ,  Shinichi SOTOME ,  Tomohiro KUKI

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11565 ,  G11C16/04

Abstract: A semiconductor storage device includes a first stacked body, a second stacked body, an intermediate insulating layer, and a plurality of columnar bodies. The intermediate insulating layer is located between a first stacked body and a second stacked body and has a thickness in the stacking direction larger than that of one insulating layer in the plurality of insulating layers of the first stacked body. The plurality of columnar bodies are provided over the first stacked body and the second stacked body, and each columnar body includes a semiconductor body, a charge storage film provided between at least one of the plurality of conductive layers and the semiconductor body, and a semiconductor film. Each of the plurality of columnar bodies include a first columnar portion formed in the first stacked body, a second columnar portion formed in the intermediate insulating layer, and a third columnar portion formed in the second stacked body. A width of the semiconductor film in the second columnar portion in a direction intersecting the stacking direction is the shortest at an upper end of the intermediate columnar portion and the longest at a lower end of the intermediate columnar portion.

公开(公告)号：US20240298445A1

公开(公告)日：2024-09-05

申请号：US18587080

申请日：2024-02-26

Applicant: Kioxia Corporation

Inventor： Yosuke MITSUNO ,  Ryouji MASUDA ,  Tatsufumi HAMADA ,  Tomohiro KUKI ,  Yusuke MORIKAWA

IPC: H10B43/27

CPC classification number: H10B43/27

Abstract: A semiconductor memory device has a chip shape. A stacked body is formed by alternately stacking, in a first direction, a plurality of first insulating layers and a plurality of first conductive layers each of which functions as a control gate of a memory cell transistor. A first columnar body extends in the first direction in the stacked body and includes a first semiconductor portion. An insulating film is provided at an end portion of the semiconductor memory device. A second columnar body extends in the first direction in the insulating film and includes a second semiconductor portion that is shorter than the first semiconductor portion in the first direction. An impurity concentration of the second semiconductor portion at a bottom portion of the second columnar body is higher than that of the first semiconductor portion at an intersection portion between the first columnar body and the first conductive layer.

公开(公告)号：US20210028189A1

公开(公告)日：2021-01-28

申请号：US16800812

申请日：2020-02-25

Applicant: KIOXIA CORPORATION

Inventor： Yosuke MITSUNO ,  Tatsufumi HAMADA ,  Shinichi SOTOME ,  Tomohiro KUKI ,  Yuya AKEBOSHI

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/28 ,  H01L27/1157

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body of first conductor layers and second conductor layers. A pillar including a semiconductor layer extends along through the stacked body in a first direction. A charge storage layer is between the conductor layers and the semiconductor layer. The semiconductor layer includes a first portion extending along the first direction from an uppermost first conductor layer to a lowermost second conductor layer and a second portion above the first portion in the first direction. The second portion has a diameter that decreases with increasing distance along the first direction from the first portion.

公开(公告)号：US20230093316A1

公开(公告)日：2023-03-23

申请号：US17654684

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Tomohiro KUKI ,  Tatsufumi HAMADA ,  Shinichi SOTOME ,  Yosuke MITSUNO

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor storage device according to an embodiment includes a stacked body and a pillar. The pillar includes an insulating core, a channel layer, and a memory film. A plurality of gate electrode layers included in the stacked body includes a plurality of first gate electrode layers and one or more second gate electrode layers. The channel layer includes a first portion and a second portion. The first portion is provided between an uppermost first gate electrode layer and the insulating core. The second portion extends from a first height to a second height. A film thickness of the second portion is greater than a film thickness of the first portion.

公开(公告)号：US20220068964A1

公开(公告)日：2022-03-03

申请号：US17204015

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Tomohiro KUKI ,  Tatsufumi HAMADA ,  Shinichi SOTOME ,  Yosuke MITSUNO ,  Muneyuki TSUDA

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/306 ,  H01L27/11556 ,  H01L27/11597

Abstract: According to one embodiment, a semiconductor storage device includes a substrate, a first electric charge holder, and a channel layer. At least a part of the first electric charge holder is curved in a first cross section along a surface of the substrate. The channel layer is inside the first electric charge holder in the first cross section. At least a part of the channel layer is curved in the first cross section. The first electric charge holder has a curvature varying in accordance with a position in the first cross section. The channel layer has a film thickness varying in accordance with the curvature of the first electric charge holder in the first cross section.

公开(公告)号：US20210366830A1

公开(公告)日：2021-11-25

申请号：US17190713

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Yosuke MITSUNO ,  Tatsufumi HAMADA ,  Shinichi SOTOME ,  Tomohiro KUKI

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

Abstract: A device includes a first semiconductor layer that includes a first region provided between a first insulating portion and first conductive layers, a second region provided between a second insulating portion and second conductive layers, and a third region provided between the first region and the second region. A first insulating layer includes a thickness (t1) from a surface in the first region to a gate insulating film. The first insulating layer includes a thickness (t2) from a surface in the second region to the gate insulating film. The first insulating layer includes a thickness (t3) from a surface in the third region to the gate insulating film, which is larger than t1-2 nanometers (nm), and larger than t2-2 nm.

公开(公告)号：US20230309303A1

公开(公告)日：2023-09-28

申请号：US17929428

申请日：2022-09-02

Applicant: Kioxia Corporation

Inventor： Yusuke MORIKAWA ,  Tatsufumi HAMADA ,  Tomohiro KUKI ,  Yosuke MITSUNO

IPC: H01L27/11582

CPC classification number: H01L27/11582

Abstract: A semiconductor memory device includes a substrate, a layer stack, and a pillar. The layer stack is in a first direction above the substrate. The pillar penetrates the layer stack in the first direction. The layer stack includes a first conductor and a first insulator on an upper surface of the first conductor along the first direction. The pillar includes a second insulator extending along an extending direction of the pillar. The second insulator includes a first part located in a first layer in which the first conductor is located and a second part located in a second layer in which the first insulator is located. The first part includes a portion thicker than the second part. A diameter of the pillar in the first layer is larger than a diameter of the pillar in the second layer.

公开(公告)号：US20230301111A1

公开(公告)日：2023-09-21

申请号：US17941987

申请日：2022-09-09

Applicant: Kioxia Corporation

Inventor： Kenta YAMADA ,  Yosuke MITSUNO ,  Takuya SUZUKI ,  Katsuyuki KITAMOTO ,  Ken KOMIYA

IPC: H01L27/11575 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/00

CPC classification number: H01L27/11575 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11582 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes a processing circuit provided on a substrate, a plurality of first electrodes connected to the processing circuit, and a plurality of second electrodes connected to the plurality of first electrodes. The semiconductor storage device also includes a memory cell array connected to the plurality of second electrodes. The memory cell array includes a block, and the block includes a string unit. Each string unit includes a plurality of memory cells, and a plurality of column-shaped parts penetrating through at least one stack body that is a stack of a plurality of electrode films between which an insulating film is interposed. The semiconductor storage device includes a slit insulating, for each string unit, a source line electrically connected to a portion of the plurality of memory cells and a source line electrically connected to another portion of the memory cells.

公开(公告)号：US20230292518A1

公开(公告)日：2023-09-14

申请号：US17842411

申请日：2022-06-16

Applicant: Kioxia Corporation

Inventor： Tatsufumi HAMADA ,  Yosuke MITSUNO ,  Tomohiro KUKI ,  Yusuke MORIKAWA

IPC: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked film alternately including first layers and second layers in a first direction, forming a hole extending in the first direction in the stacked film, and forming a first insulator on a side face of the stacked film in the hole. The method further includes removing the first insulator in the hole to expose a first part of the side face of the stacked film at a predetermined height in the first direction of the hole and to expose a side face of the first insulator remaining on a second part of the side face of the stacked film at the predetermined height. The method further includes forming a second insulator on the first part of the side face of the stacked film and the side face of the remaining first insulator in the hole.