公开(公告)号：US20140348192A1

公开(公告)日：2014-11-27

申请号：US14350404

申请日：2012-10-08

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Armand Pruijmboom ,  Raimond Louis Dumoulin ,  Michael Miller

IPC: H01S5/022 ,  H01S5/028 ,  H01S5/30 ,  H01S5/024 ,  H01S5/42

CPC classification number: H01S5/02236 ,  H01L24/04 ,  H01L24/05 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01S5/02272 ,  H01S5/02469 ,  H01S5/028 ,  H01S5/3013 ,  H01S5/423 ,  H01L2924/00

Abstract: The present invention relates to a method of assembling VCSEL chips (1) on a sub-mount (2). A de-wetting layer (13) is deposited on a connecting side of the VCSEL chips (1) which is to be connected to the sub-mount (2). A further de-wetting layer (13) is deposited on a connecting side of the sub-mount (2) which is to be connected to the VCSEL chips (1). The de-wetting layers (13) are deposited with a patterned design or are patterned after depositing to define connecting areas (21) on the sub-mount (2) and the VCSEL chips (1). A solder (15) is applied to the connecting areas (21) of at least one of the two connecting sides. The VCSEL chips (1) are placed on the sub-mount (2) and soldered to the sub-mount (2) to electrically and mechanically connect the VCSEL chips (1) and the sub-mount (2). With the proposed method a high alignment accuracy of the VCSEL chips (1) on the sub-mount (2) is achieved without time consuming measures.

Abstract translation: 本发明涉及一种将VCSEL芯片（1）组装在子座（2）上的方法。 在VCSEL芯片（1）的与子座（2）连接的连接侧上沉积去湿层（13）。 进一步的去润湿层（13）沉积在子座（2）的连接到VCSEL芯片（1）的连接侧上。 去湿层（13）以图案化设计沉积，或者在沉积之后被图案化以限定子安装座（2）和VCSEL芯片（1）上的连接区域（21）。 将焊料（15）施加到两个连接侧中的至少一个的连接区域（21）。 将VCSEL芯片（1）放置在子座（2）上并焊接到子座（2）以电和机械地连接VCSEL芯片（1）和子座（2）。 利用所提出的方法，实现了子安装座（2）上的VCSEL芯片（1）的高对准精度，而不需要耗费时间的措施。

公开(公告)号：US09099834B2

公开(公告)日：2015-08-04

申请号：US14396655

申请日：2013-04-11

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Stephan Gronenborn ,  Michael Miller

IPC: H01S3/04 ,  H01S5/04 ,  H01S5/14 ,  H01S5/42 ,  G02B17/06 ,  H01S3/08 ,  H01S5/00 ,  H01S5/022 ,  H01S5/024 ,  H01S5/026 ,  H01S5/183

CPC classification number: H01S5/041 ,  G02B17/06 ,  H01S3/08068 ,  H01S5/0071 ,  H01S5/02252 ,  H01S5/02476 ,  H01S5/026 ,  H01S5/141 ,  H01S5/18305 ,  H01S5/18388 ,  H01S5/18397 ,  H01S5/423

Abstract: The present invention relates to an optically pumped vertical external-cavity surface-emitting laser device comprising at least one VECSEL (200) and several pump laser diodes (300). The pump laser diodes (300) are arranged to optically pump the active region (108) of the VECSEL (200) by reflection of pump radiation (310) at a mirror element (400). The mirror element (400) is arranged on the optical axis (210) of the VECSEL (200) and is designed to concentrate the pump radiation (310) in the active region (108) and to form at the same time the external mirror of the VECSEL (200). The proposed device avoids time consuming adjustment of the pump lasers relative to the active region of the VECSEL and allows a very compact design of the laser device.

Abstract translation: 本发明涉及一种光泵浦垂直外腔表面发射激光器件，其包括至少一个VECSEL（200）和多个泵激光二极管（300）。 泵浦激光二极管（300）被布置成通过在反射镜元件（400）处的泵辐射（310）的反射来光学地泵浦VECSEL（200）的有源区域（108）。 反射镜元件（400）设置在VECSEL（200）的光轴（210）上，并被设计成将泵浦辐射（310）集中在有源区域（108）中并且同时形成外部反射镜 VECSEL（200）。 所提出的装置避免了泵激光器相对于VECSEL的有源区域的耗时调整，并允许激光装置的非常紧凑的设计。

公开(公告)号：US20150071320A1

公开(公告)日：2015-03-12

申请号：US14382793

申请日：2013-02-22

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Stephan Gronenborn ,  Armand Pruijmboom ,  Raimond Louis Dumoulin ,  Michael Miller

IPC: H01S5/42 ,  H01S5/00 ,  H01S5/40 ,  H01S5/183

CPC classification number: H01S5/423 ,  H01S5/005 ,  H01S5/0216 ,  H01S5/0217 ,  H01S5/02288 ,  H01S5/183 ,  H01S5/4018 ,  H01S5/4025

Abstract: The invention describes a method of manufacturing a VCSEL module (100) comprising at least one VCSEL chip (33) with an upper side (U) and a lower side (L) and with a plurality of VCSEL units (55) on a common carrier structure (35), the VCSEL units (55) comprising a first doped layer (50) of a first type facing towards the lower side (L) and a second doped layer (23) of a second type facing towards the upper side (U). The method comprises the steps of dividing the VCSEL chip (33) into a plurality of subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) with at least one VCSEL unit (55) each, electrically connecting at least some of the subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) in series. The invention also describes a VCSEL module (100) manufactured in such process.

Abstract translation: 本发明描述了制造VCSEL模块（100）的方法，该VCSEL模块（100）包括至少一个具有上侧（U）和下侧（L）的VCSEL芯片（33），并且在公共载体上具有多个VCSEL单元（55） 结构（35），包括面向下侧（L）的第一类型的第一掺杂层（50）和面向上侧（U）的第二类型的第二掺杂层（23）的VCSEL单元（55） ）。 该方法包括以下步骤：用至少一个VCSEL单元（55）将VCSEL芯片（33）分成多个子阵列（39a，39b，39c，39d，39e，39f，39g，39h，39i），电连接 串联的至少一些子阵列（39a，39b，39c，39d，39e，39f，39g，39h，39i）。 本发明还描述了以这种方法制造的VCSEL模块（100）。

公开(公告)号：US20180278024A1

公开(公告)日：2018-09-27

申请号：US15762277

申请日：2016-09-22

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Stephan Gronenborn ,  Michael Miller ,  Peter Dannberg ,  Mark Schuermann ,  Holger Moench

IPC: H01S5/183 ,  H01S5/42 ,  H01S5/042 ,  H01S5/028

CPC classification number: H01S5/18388 ,  H01S5/0042 ,  H01S5/0201 ,  H01S5/0283 ,  H01S5/0421 ,  H01S5/423 ,  H01S2301/17

Abstract: The invention describes a light emitting device (100). The light emitting device (100) comprises at least one light emitting structure (110), at least one processing layer (120) and at least one optical structure (130). The optical structure (130) comprises at least one material processed by means of processing light (150). The at least one processing layer (120) is arranged to reduce reflection of the processing light (150) in a direction of the optical structure (130) at least by 50%, preferably at least by 80%, more preferably at least by 95% and most preferably at least by 99% during processing of the material by means of the processing light (150). It is a basic idea of the present invention to incorporate a non- or low-reflective processing layer (120) on top of a light emitting structure (110) like a VCSEL array in order to enable on wafer processing of light emitting structures (130) like microlens arrays. The invention further describes a method of manufacturing such a light emitting device (100).

公开(公告)号：US09065235B2

公开(公告)日：2015-06-23

申请号：US14350404

申请日：2012-10-08

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Armand Pruijmboom ,  Raimond Louis Dumoulin ,  Michael Miller

IPC: H01S5/022 ,  H01S5/028 ,  H01S5/30 ,  H01S5/42 ,  H01S5/024 ,  H01L23/00

CPC classification number: H01S5/02236 ,  H01L24/04 ,  H01L24/05 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01S5/02272 ,  H01S5/02469 ,  H01S5/028 ,  H01S5/3013 ,  H01S5/423 ,  H01L2924/00

Abstract: The present invention relates to a method of assembling VCSEL chips (1) on a sub-mount (2). A de-wetting layer (13) is deposited on a connecting side of the VCSEL chips (1) which is to be connected to the sub-mount (2). A further de-wetting layer (13) is deposited on a connecting side of the sub-mount (2) which is to be connected to the VCSEL chips (1). The de-wetting layers (13) are deposited with a patterned design or are patterned after depositing to define connecting areas (21) on the sub-mount (2) and the VCSEL chips (1). A solder (15) is applied to the connecting areas (21) of at least one of the two connecting sides. The VCSEL chips (1) are placed on the sub-mount (2) and soldered to the sub-mount (2) to electrically and mechanically connect the VCSEL chips (1) and the sub-mount (2). With the proposed method a high alignment accuracy of the VCSEL chips (1) on the sub-mount (2) is achieved without time consuming measures.

Abstract translation: 本发明涉及一种将VCSEL芯片（1）组装在子座（2）上的方法。 在VCSEL芯片（1）的与子座（2）连接的连接侧上沉积去湿层（13）。 进一步的去润湿层（13）沉积在子座（2）的连接到VCSEL芯片（1）的连接侧上。 去湿层（13）以图案化设计沉积，或者在沉积之后被图案化以限定子安装座（2）和VCSEL芯片（1）上的连接区域（21）。 将焊料（15）施加到两个连接侧中的至少一个的连接区域（21）。 将VCSEL芯片（1）放置在子安装座（2）上并焊接到子安装座（2）以电气和机械地连接VCSEL芯片（1）和子安装座（2）。 利用所提出的方法，实现了子安装座（2）上的VCSEL芯片（1）的高对准精度，而不需要耗费时间的措施。

公开(公告)号：US09172213B2

公开(公告)日：2015-10-27

申请号：US14382793

申请日：2013-02-22

Applicant: KONINKLIJKE PHILIPS N.V.

Inventor： Stephan Gronenborn ,  Armand Pruijmboom ,  Raimond Louis Dumoulin ,  Michael Miller

IPC: H01S5/00 ,  H01S5/42 ,  H01S5/183 ,  H01S5/40 ,  H01S5/02 ,  H01S5/022

CPC classification number: H01S5/423 ,  H01S5/005 ,  H01S5/0216 ,  H01S5/0217 ,  H01S5/02288 ,  H01S5/183 ,  H01S5/4018 ,  H01S5/4025

Abstract: The invention describes a method of manufacturing a VCSEL module (100) comprising at least one VCSEL chip (33) with an upper side (U) and a lower side (L) and with a plurality of VCSEL units (55) on a common carrier structure (35), the VCSEL units (55) comprising a first doped layer (50) of a first type facing towards the lower side (L) and a second doped layer (23) of a second type facing towards the upper side (U). The method comprises the steps of dividing the VCSEL chip (33) into a plurality of subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) with at least one VCSEL unit (55) each, electrically connecting at least some of the subarrays (39a, 39b, 39c, 39d, 39e, 39f, 39g, 39h, 39i) in series. The invention also describes a VCSEL module (100) manufactured in such process.

Abstract translation: 本发明描述了制造VCSEL模块（100）的方法，该VCSEL模块（100）包括至少一个具有上侧（U）和下侧（L）的VCSEL芯片（33），并且在公共载体上具有多个VCSEL单元（55） 结构（35），包括面向下侧（L）的第一类型的第一掺杂层（50）和面向上侧（U）的第二类型的第二掺杂层（23）的VCSEL单元（55） ）。 该方法包括以下步骤：用至少一个VCSEL单元（55）将VCSEL芯片（33）分成多个子阵列（39a，39b，39c，39d，39e，39f，39g，39h，39i），电连接 串联的至少一些子阵列（39a，39b，39c，39d，39e，39f，39g，39h，39i）。 本发明还描述了以这种方法制造的VCSEL模块（100）。