公开(公告)号：US20190273135A1

公开(公告)日：2019-09-05

申请号：US16100272

申请日：2018-08-10

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Chiharu Ota ,  Tatsunori Sakano ,  Tatsuo Shimizu ,  Ryosuke Iijima

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L21/02

摘要： According to one embodiment, a semiconductor device includes a first element. The first element includes a first electrode, a second electrode and first to fourth semiconductor regions. The second electrode includes a first conductive region and a second conductive region. The first semiconductor region is provided between the first electrode and the first conductive region and between the first electrode and the second conductive region. The second semiconductor region includes a first partial region and a second partial region. The first partial region is provided between the first electrode and the first conductive region. The second partial region is provided between the first electrode and the second conductive region. The third semiconductor region is provided between the second partial region and the second conductive region. The fourth semiconductor region is provided between the third semiconductor region and the second conductive region.

公开(公告)号：US09111844B2

公开(公告)日：2015-08-18

申请号：US14448287

申请日：2014-07-31

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Tatsuo Shimizu ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/167 ,  H01L21/02 ,  H01L29/739

CPC分类号： H01L29/167 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66477 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7802

摘要： A semiconductor device of an embodiment includes: an n-type first SiC epitaxial layer; a p-type second SiC epitaxial layer provided on the first SiC epitaxial layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 1.0; n-type first and second SiC regions provided in the surface of the second SiC epitaxial layer; a gate insulating film; a gate electrode; a first electrode provided on the second SiC region; and a second electrode provided on the opposite side from the first electrode.

摘要翻译： 实施例的半导体器件包括：n型第一SiC外延层; 设置在第一SiC外延层上并包含p型杂质和n型杂质的p型第二SiC外延层，p型杂质为元素A，n型杂质为元素D， 元素A和形成Al，Ga或In和N的组合的元素D和/或B和P的组合，元素D的浓度与组合中的元素A的浓度之比（s ）高于0.33但低于1.0; 设置在第二SiC外延层表面的n型第一和第二SiC区域; 栅极绝缘膜; 栅电极; 设置在所述第二SiC区域上的第一电极; 以及设置在与第一电极相对的一侧的第二电极。

公开(公告)号：US08933465B2

公开(公告)日：2015-01-13

申请号：US14205854

申请日：2014-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Chiharu Ota ,  Tatsuo Shimizu ,  Johji Nishio ,  Takashi Shinohe

IPC分类号： H01L31/0312 ,  H01L29/16 ,  H01L29/66 ,  H01L29/872 ,  H01L29/167 ,  H01L29/45 ,  H01L29/47 ,  H01L29/06

CPC分类号： H01L29/1608 ,  H01L29/0619 ,  H01L29/167 ,  H01L29/45 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/872

摘要： A semiconductor device of an embodiment includes an n-type SiC substrate, an n-type SiC layer formed on the SiC substrate; a p-type first SiC region formed in the surface of the SiC layer and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al, Ga, or In and N, and/or a combination of B and P, the ratio of the concentration of the element D to the concentration of the element A in the combination(s) being higher than 0.33 but lower than 0.995, the concentration of the element A forming part of the combination(s) being not lower than 1×1017 cm−3 and not higher than 1×1022 cm−3, a first electrode, and a second electrode.

摘要翻译： 实施例的半导体器件包括n型SiC衬底，形成在SiC衬底上的n型SiC层; 在SiC层的表面形成有p型杂质和n型杂质的p型第一SiC区域，p型杂质为元素A，n型杂质为元素D， 元素A和元素D是Al，Ga或In和N的组合和/或B和P的组合，元素D的浓度与组合中的元素A的浓度之比（s ）高于0.33但低于0.995，构成组合部分的元素A的浓度不低于1×1017cm-3且不高于1×1022cm-3，第一电极和 第二电极。

公开(公告)号：US11973116B2

公开(公告)日：2024-04-30

申请号：US17643558

申请日：2021-12-09

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Johji Nishio ,  Chiharu Ota

IPC分类号： H01L29/16 ,  H01L29/04 ,  H01L29/167 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/1608 ,  H01L29/045 ,  H01L29/167 ,  H01L29/7802 ,  H01L29/861

摘要： According to one embodiment, a semiconductor device includes a silicon carbide member. The silicon carbide member includes an operating region including at least one of a diode or a transistor, and a first element region including at least one element selected from the group consisting of Ar, V, Al and B. The first element region includes a first region and a second region. A first direction from the first region toward the second region is along a [1-100] direction of the silicon carbide member. The operating region is between the first region and the second region in the first direction. The first element region does not include a region overlapping the operating region in a second direction along a [11-20] direction of the silicon carbide member. Or the first element region includes a third region overlapping the operating region in the second direction.

公开(公告)号：US11848211B2

公开(公告)日：2023-12-19

申请号：US18111923

申请日：2023-02-21

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Yukio Nakabayashi ,  Johji Nishio ,  Chiharu Ota ,  Toshihide Ito

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/16 ,  H02P27/06 ,  B61C3/00 ,  B60L50/51 ,  B66B11/04

CPC分类号： H01L21/045 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02271 ,  H01L21/046 ,  H01L21/049 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/51 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  B60L50/51 ,  B60L2210/42 ,  B61C3/00 ,  B66B11/043 ,  H02P27/06

摘要： A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm−3 and a carbon concentration at the first position is equal to or less than 1×1018 cm−3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm−3.

公开(公告)号：US11621167B2

公开(公告)日：2023-04-04

申请号：US17568761

申请日：2022-01-05

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Yukio Nakabayashi ,  Johji Nishio ,  Chiharu Ota ,  Toshihide Ito

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/16 ,  H02P27/06 ,  B61C3/00 ,  B60L50/51 ,  B66B11/04

摘要： A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm−3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm−3 and a carbon concentration at the first position is equal to or less than 1×1018 cm−3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm−3.

公开(公告)号：US09324787B2

公开(公告)日：2016-04-26

申请号：US14467146

申请日：2014-08-25

申请人： Kabushiki Kaisha Toshiba

发明人： Chiharu Ota ,  Tatsuo Shimizu ,  Johji Nishio ,  Takashi Shinohe

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/36 ,  H01L29/861 ,  H01L29/872 ,  H01L29/16 ,  H01L29/167 ,  H01L29/66 ,  H01L29/04

CPC分类号： H01L29/0634 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/8613 ,  H01L29/872

摘要： According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, and a first electrode. The first semiconductor region is of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, and is of a second conductivity type. The third semiconductor region is provided on the second semiconductor region, and is of the second conductivity type. The third semiconductor region contains a first impurity of the first conductivity type and a second impurity of the second conductivity type, and satisfies 1

摘要翻译： 根据一个实施例，半导体器件包括第一半导体区域，第二半导体区域，第三半导体区域和第一电极。 第一半导体区域是第一导电类型。 第二半导体区域设置在第一半导体区域上，并且是第二导电类型。 第三半导体区域设置在第二半导体区域上，并且是第二导电类型。 第三半导体区域包含第一导电类型的第一杂质和第二导电类型的第二杂质，并且满足1

公开(公告)号：US09236434B2

公开(公告)日：2016-01-12

申请号：US14339165

申请日：2014-07-23

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Chiharu Ota ,  Takashi Shinohe ,  Makoto Mizukami ,  Johji Nishio

IPC分类号： H01L29/868 ,  H01L29/16 ,  H01L29/66 ,  H01L29/861 ,  H01L29/872 ,  H01L21/02 ,  H01L21/265 ,  H01L29/47

CPC分类号： H01L29/1608 ,  H01L21/02529 ,  H01L21/26513 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor device according to an embodiment includes a first-conductive-type semiconductor substrate; a first-conductive-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductive-type second semiconductor layer epitaxially formed on the first semiconductor layer; and a second-conductive-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer. The semiconductor device also includes a recess formed in the third semiconductor layer, and at least a corner portion of a side face and a bottom surface is located in the second semiconductor layer. The semiconductor device also includes a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode while being in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substrate.

摘要翻译： 根据实施例的半导体器件包括第一导电型半导体衬底; 形成在半导体衬底上的第一导电型第一半导体层，其杂质浓度低于半导体衬底的杂质浓度; 外延形成在第一半导体层上的第二导电型第二半导体层; 以及外延形成在所述第二半导体层上，并且具有比所述第二半导体层的杂质浓度高的杂质浓度的第二导电型第三半导体层。 半导体器件还包括形成在第三半导体层中的凹部，并且至少侧面和底面的角部位于第二半导体层中。 半导体器件还包括与第三半导体层接触的第一电极; 第二电极，其与所述第一电极连接，同时在所述凹部的底表面处与所述第二半导体层接触; 以及与半导体衬底的下表面接触的第三电极。

公开(公告)号：US20140284622A1

公开(公告)日：2014-09-25

申请号：US14205914

申请日：2014-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo SHIMIZU ,  Takashi Shinohe ,  Johji Nishio ,  Chiharu Ota

IPC分类号： H01L29/16 ,  H01L29/49 ,  H01L21/04

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/49 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/868

摘要： A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm−3 and not higher than 1×1022 cm−3.

摘要翻译： 实施例的半导体器件包括含有p型杂质和n型杂质的p型SiC杂质区。 当p型杂质是元素A，n型杂质是元素D时，元素A和元素D形成Al（铝），Ga（镓）或In（铟）和N（ 氮）和/或B（硼）和P（磷）的组合。 元素D的浓度与上述组合中的元素A的浓度的比例高于0.33但低于0.995，构成上述组合的一部分的元素A的浓度不低于1×1018cm -3且不高于1×1022cm-3。

公开(公告)号：US11443946B2

公开(公告)日：2022-09-13

申请号：US17004264

申请日：2020-08-27

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Johji Nishio ,  Chiharu Ota

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L29/04 ,  C30B29/36 ,  C30B23/02 ,  C30B25/20 ,  C23C14/06 ,  C23C14/58 ,  C23C16/32 ,  C23C16/56 ,  H01L29/16 ,  H01L29/78 ,  H01L29/861 ,  H01L29/739

摘要： According to one embodiment, a method for manufacturing a silicon carbide base body is disclosed. The method can include preparing a first base body including silicon carbide. The first base body includes a first base body surface tilted with respect to a (0001) plane of the first base body. A first line segment where the first base body surface and the (0001) plane of the first base body intersect is along a [11-20] direction of the first base body. The method can include forming a first layer at the first base body surface. The first layer includes silicon carbide. The method can include removing a portion of the first layer. The first-layer surface is tilted with respect to a (0001) plane of the first layer. A second line segment where the first-layer surface and the (0001) plane of the first layer intersect is along a [−1100] direction.