公开(公告)号：US10177251B2

公开(公告)日：2019-01-08

申请号：US15891935

申请日：2018-02-08

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Takashi Shinohe ,  Ryosuke Iijima

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/417 ,  H01L29/08 ,  H01L29/36 ,  H01L29/49

摘要： A semiconductor device according to an embodiment includes a silicon carbide layer having a first plane and a second plane; a source electrode; a drain electrode; first and second gate electrodes located; an n-type drift region and a p-type body region; n-type first and second source regions; a p-type first silicon carbide region and p-type second silicon carbide region having a p-type impurity concentration higher than the body region; first and second gate insulating layers; a p-type third silicon carbide region contacting the first silicon carbide region, a first n-type portion being located between the first gate insulating layer and the third silicon carbide region; and a p-type fourth silicon carbide region contacting the second silicon carbide region, a second n-type portion being located between the second gate insulating layer and the fourth silicon carbide region.

公开(公告)号：US09741798B2

公开(公告)日：2017-08-22

申请号：US14871053

申请日：2015-09-30

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Takashi Shinohe

IPC分类号： H01L29/16 ,  H01L29/423 ,  H01L29/51 ,  H01L29/78 ,  H01L21/04 ,  H01L27/04 ,  H01L29/66 ,  H01L29/792 ,  H01L29/739

CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/4234 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/792

摘要： According to one embodiment, a semiconductor device includes a structure, an insulating film, a control electrode, first and second electrodes. The structure has a first surface, and includes a first, a second, and a third semiconductor region. The structure has a portion including the first, second, and third semiconductor regions arranged in a first direction along the first surface. The insulating film is provided on the first surface. The control electrode is provided on the insulating film. The first electrode is electrically connected to the third semiconductor region. The second electrode is electrically connected to the first semiconductor region. The insulating film includes a charge trap region. A bias voltage is applied to the first and second electrodes, and includes a shift voltage. The shift voltage shifts a reference potential of a voltage applied to the first and second electrodes by a certain voltage.

公开(公告)号：US09564802B2

公开(公告)日：2017-02-07

申请号：US14478445

申请日：2014-09-05

申请人： Kabushiki Kaisha Toshiba

发明人： Kazuto Takao ,  Takashi Shinohe

IPC分类号： H02M7/537 ,  H02M3/155 ,  H02M1/44 ,  H02M7/5387

CPC分类号： H02M3/155 ,  H02M1/44 ,  H02M7/5387 ,  H02M2003/1555 ,  Y02B70/1441

摘要： An electric power conversion device of an embodiment includes the electric power conversion device expressed as an equivalent circuit including, a power supply, a first parasitic inductance, a first diode; a second parasitic inductance connected to the first diode in series, a second diode connected to the first diode in parallel, a third parasitic inductance connected to the second diode in series, a switching element, a gate circuit, and a load. The equivalent circuit includes a first circuit loop and a second circuit loop. The first circuit loop includes the power supply, the first parasitic inductance, the first diode, the second parasitic inductance, the switching element, and the gate circuit. The second circuit loop includes the power supply, the first parasitic inductance, the second diode, the third parasitic inductance, the switching element, and the gate circuit.

摘要翻译： 一个实施例的电力转换装置包括表示为等效电路的电力转换装置，包括电源，第一寄生电感，第一二极管; 串联连接到第一二极管的第二寄生电感，并联连接到第一二极管的第二二极管，串联连接到第二二极管的第三寄生电感，开关元件，门电路和负载。 等效电路包括第一电路回路和第二回路回路。 第一电路回路包括电源，第一寄生电感，第一二极管，第二寄生电感，开关元件和门电路。 第二电路回路包括电源，第一寄生电感，第二二极管，第三寄生电感，开关元件和门电路。

公开(公告)号：US09419517B2

公开(公告)日：2016-08-16

申请号：US14478445

申请日：2014-09-05

申请人： Kabushiki Kaisha Toshiba

发明人： Kazuto Takao ,  Takashi Shinohe

IPC分类号： H02M7/537 ,  H02M3/155 ,  H02M1/44 ,  H02M7/5387

摘要： An electric power conversion device of an embodiment includes the electric power conversion device expressed as an equivalent circuit including, a power supply, a first parasitic inductance, a first diode; a second parasitic inductance connected to the first diode in series, a second diode connected to the first diode in parallel, a third parasitic inductance connected to the second diode in series, a switching element, a gate circuit, and a load. The equivalent circuit includes a first circuit loop and a second circuit loop. The first circuit loop includes the power supply, the first parasitic inductance, the first diode, the second parasitic inductance, the switching element, and the gate circuit. The second circuit loop includes the power supply, the first parasitic inductance, the second diode, the third parasitic inductance, the switching element, and the gate circuit.

公开(公告)号：US09412823B2

公开(公告)日：2016-08-09

申请号：US14855669

申请日：2015-09-16

申请人： Kabushiki Kaisha Toshiba

发明人： Chiharu Ota ,  Tatsuo Shimizu ,  Johji Nishio ,  Takashi Shinohe

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/167 ,  H01L21/02 ,  H01L21/04 ,  H01L29/78 ,  H01L29/872 ,  H01L29/808 ,  H01L29/868 ,  H01L29/739 ,  H01L29/861 ,  H01L29/36

CPC分类号： H01L29/1608 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/046 ,  H01L29/167 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor device of an embodiment includes, an n-type SiC substrate that has first and second faces, and contains a p-type impurity and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus), the ratio of the concentration of the element A to the concentration of the element D in the combination(s) being higher than 0.40 but lower than 0.95, the concentration of the element D forming the combination(s) being not lower than 1×1018 cm−3 and not higher than 1×1022 cm−3, an SiC layer formed on the first face, a first electrode formed on the first face side, and a second electrode formed on the second face.

摘要翻译： 实施方式的半导体装置具有：具有第一面和第二面的n型SiC衬底，含有p型杂质和n型杂质，p型杂质为元素A，n型杂质 作为元素D，元素A和元素D是Al（铝），Ga（镓）或In（铟）和N（氮）的组合，和/或B（硼）和P（ 磷），组合物中元素A浓度与元素D的浓度的比例高于0.40但小于0.95时，形成组合的元素D的浓度不低于 1×1018cm-3且不高于1×1022cm-3，形成在第一面上的SiC层，形成在第一表面侧上的第一电极和形成在第二面上的第二电极。

公开(公告)号：US09373686B2

公开(公告)日：2016-06-21

申请号：US14167295

申请日：2014-01-29

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Tatsuo Shimizu ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L29/16 ,  H01L21/04 ,  H01L29/34 ,  H01L29/66 ,  H01L29/861 ,  H01L29/161 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L29/161 ,  H01L29/34 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/8611 ,  H01L29/8613

摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type made of silicon carbide; and a second semiconductor layer of a second conductivity type made of silicon carbide, placed in junction with the first semiconductor layer, and containing an electrically inactive element.

摘要翻译： 根据一个实施例，半导体器件包括由碳化硅制成的第一导电类型的第一半导体层; 以及由碳化硅制成的第二导电类型的第二半导体层，放置在与第一半导体层的结合处，并且包含电非活性元件。

公开(公告)号：US20160005605A1

公开(公告)日：2016-01-07

申请号：US14690968

申请日：2015-04-20

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Tatsuo Shimizu ,  Takashi Shinohe

IPC分类号： H01L21/04 ,  H01L29/16 ,  H01L29/78 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/046 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/8613

摘要： In a manufacturing method for a semiconductor device according to an embodiment, a first heat treatment to anneal or oxidize an SiC layer in an atmosphere where a gas including carbon (C) exists is applied. Further, the semiconductor device according to the embodiment includes: an SiC substrate having a first surface and a second surface; a first conductivity type SiC layer disposed on the first surface side of the SiC substrate, and including a low level density region having Z1/2 level density of 1×1011 cm−3 or less measured by deep level transient spectroscopy (DLTS); a second conductivity type SiC region disposed on a surface of the SiC layer; a first electrode disposed on the SiC region; and a second electrode disposed on the second surface side of the SiC substrate.

摘要翻译： 在根据实施例的半导体器件的制造方法中，施加在存在碳（C）的气体的气氛中退火或氧化SiC层的第一热处理。 另外，本实施方式的半导体装置具备：具有第一表面和第二表面的SiC衬底; 设置在SiC衬底的第一表面侧的第一导电型SiC层，并且包括通过深层瞬态光谱法（DLTS）测量的Z1 / 2电平密度为1×1011cm-3或更低的低电平密度区域; 设置在所述SiC层的表面上的第二导电型SiC区域; 设置在所述SiC区域上的第一电极; 以及设置在所述SiC衬底的第二表面侧上的第二电极。

公开(公告)号：US09093362B2

公开(公告)日：2015-07-28

申请号：US14205887

申请日：2014-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Johji Nishio ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L31/0312 ,  H01L21/265 ,  H01L21/00 ,  H01L29/16 ,  H01L21/04 ,  C30B29/36 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1608 ,  C30B29/36 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7827

摘要： A semiconductor device of an embodiment includes an n-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element A to the concentration of the element D in the above combination is higher than 0.40 but lower than 0.95, and the concentration of the element D forming the above combination is not lower than 1×1018 cm−3 and not higher than 1×1022 cm−3.

摘要翻译： 实施例的半导体器件包括含有p型杂质和n型杂质的n型SiC杂质区。 当p型杂质是元素A，n型杂质是元素D时，元素A和元素D形成Al（铝），Ga（镓）或In（铟）和N（ 氮）和/或B（硼）和P（磷）的组合。 元素A的浓度与上述组合中的元素D的浓度的比例高于0.40但低于0.95，构成上述组合的元素D的浓度不低于1×1018cm-3 不高于1×1022cm-3。

公开(公告)号：US20150085548A1

公开(公告)日：2015-03-26

申请号：US14478445

申请日：2014-09-05

申请人： Kabushiki Kaisha Toshiba

发明人： Kazuto TAKAO ,  Takashi Shinohe

IPC分类号： H02M7/537

CPC分类号： H02M3/155 ,  H02M1/44 ,  H02M7/5387 ,  H02M2003/1555 ,  Y02B70/1441

摘要： An electric power conversion device of an embodiment includes the electric power conversion device expressed as an equivalent circuit including, a power supply, a first parasitic inductance, a first diode; a second parasitic inductance connected to the first diode in series, a second diode connected to the first diode in parallel, a third parasitic inductance connected to the second diode in series, a switching element, a gate circuit, and a load. The equivalent circuit includes a first circuit loop and a second circuit loop. The first circuit loop includes the power supply, the first parasitic inductance, the first diode, the second parasitic inductance, the switching element, and the gate circuit. The second circuit loop includes the power supply, the first parasitic inductance, the second diode, the third parasitic inductance, the switching element, and the gate circuit.

摘要翻译： 一个实施例的电力转换装置包括表示为等效电路的电力转换装置，包括电源，第一寄生电感，第一二极管; 串联连接到第一二极管的第二寄生电感，并联连接到第一二极管的第二二极管，串联连接到第二二极管的第三寄生电感，开关元件，门电路和负载。 等效电路包括第一电路回路和第二回路回路。 第一电路回路包括电源，第一寄生电感，第一二极管，第二寄生电感，开关元件和门电路。 第二电路回路包括电源，第一寄生电感，第二二极管，第三寄生电感，开关元件和门电路。

公开(公告)号：US08933464B2

公开(公告)日：2015-01-13

申请号：US14205792

申请日：2014-03-12

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Tatsuo Shimizu ,  Chiharu Ota ,  Takashi Shinohe

IPC分类号： H01L31/0312 ,  H01L29/16 ,  H01L21/02 ,  C30B29/36

CPC分类号： H01L29/1608 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/66068 ,  H01L29/7827

摘要： An SiC epitaxial wafer of an embodiment includes, an SiC substrate, and a p-type first SiC epitaxial layer that is formed on the SiC substrate and contains a p-type impurity and an n-type impurity. An element A and an element D being a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus) when the p-type impurity is the element A and the n-type impurity is the element D. The ratio of the concentration of the element D to the concentration of the element A in the combination(s) is higher than 0.33 but lower than 1.0.

摘要翻译： 实施方案的SiC外延晶片包括SiC衬底和形成在SiC衬底上并包含p型杂质和n型杂质的p型第一SiC外延层。 元素A和元素D是Al（铝），Ga（镓）或In（铟）和N（氮）的组合，和/或B（硼）和P（磷）的组合，当p 型杂质是元素A，n型杂质是元素D.组合（D）中元素D的浓度与元素A的浓度之比高于0.33但低于1.0。