公开(公告)号：US08748859B2

公开(公告)日：2014-06-10

申请号：US13441805

申请日：2012-04-06

申请人： Kang-Jay Hsia ,  Christopher J Petti ,  Calvin K Li

发明人： Kang-Jay Hsia ,  Christopher J Petti ,  Calvin K Li

IPC分类号： H01L29/02

CPC分类号： H01L27/1021

摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

摘要翻译： 提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。 诸如无源元件存储单元的两端器件可以包括与反熔丝和/或其他状态改变元件串联的二极管操作元件。 这些装置在上下导体组的交点处使用支柱结构形成。 通过在轨道堆叠中的每个支柱的一个导体上形成二极管的一部分来减小柱结构的高度。 一个实施例中的二极管可以包括第一导电类型的第一二极管部件和第二导电类型的第二二极管部件。 二极管部件之一的一部分被分成第一和第二部分，其中一部分形成在轨道堆叠中，其中与在轨道堆叠处使用柱形成的其他二极管共用。

公开(公告)号：US20120187361A1

公开(公告)日：2012-07-26

申请号：US13441805

申请日：2012-04-06

申请人： Kang-Jay Hsia ,  Christopher J. Petti ,  Calvin K. Li

发明人： Kang-Jay Hsia ,  Christopher J. Petti ,  Calvin K. Li

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L27/1021

摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

摘要翻译： 提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。 诸如无源元件存储单元的两端器件可以包括与反熔丝和/或其他状态改变元件串联的二极管操作元件。 这些装置在上下导体组的交点处使用支柱结构形成。 通过在轨道堆叠中的每个支柱的一个导体上形成二极管的一部分来减小柱结构的高度。 一个实施例中的二极管可以包括第一导电类型的第一二极管部件和第二导电类型的第二二极管部件。 二极管部件之一的一部分被分成第一和第二部分，其中一部分形成在轨道堆叠中，其中与在轨道堆叠处使用柱形成的其他二极管共用。

公开(公告)号：US07927990B2

公开(公告)日：2011-04-19

申请号：US11771137

申请日：2007-06-29

申请人： Kang-Jay Hsia ,  Calvin K Li ,  Christopher J Petti

发明人： Kang-Jay Hsia ,  Calvin K Li ,  Christopher J Petti

IPC分类号： H01L21/20

CPC分类号： H01L21/76838 ,  H01L21/76834 ,  H01L27/1021

摘要： A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.

摘要翻译： 提供了一种形成密集间隔的金属线的方法。 通过蚀刻第一金属层形成第一组金属线。 平坦地沉积在第一金属线上的薄介电层。 第二金属沉积在薄介电层上，填充第一金属线之间的间隙。 第二金属层被平坦化以形成插入在第一金属线之间的第二金属线，在基本上平坦的表面处共存薄介电层和第二金属层。 在一些实施例中，平面化继续移除第一金属线的薄电介质覆盖顶部，在基本上平坦的表面处将第一金属线和由薄介电层隔开的第二金属线并入。

公开(公告)号：US08154005B2

公开(公告)日：2012-04-10

申请号：US12139435

申请日：2008-06-13

申请人： Kang-Jay Hsia ,  Christopher J. Petti ,  Calvin K. Li

发明人： Kang-Jay Hsia ,  Christopher J. Petti ,  Calvin K. Li

IPC分类号： H01L29/06

CPC分类号： H01L27/1021

摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

摘要翻译： 提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。 诸如无源元件存储单元的两端器件可以包括与反熔丝和/或其他状态改变元件串联的二极管操作元件。 这些装置在上下导体组的交点处使用支柱结构形成。 通过在轨道堆叠中的每个支柱的一个导体上形成二极管的一部分来减小柱结构的高度。 一个实施例中的二极管可以包括第一导电类型的第一二极管部件和第二导电类型的第二二极管部件。 二极管部件之一的一部分被分成第一和第二部分，其中一部分形成在轨道堆叠中，其中与在轨道堆叠处使用柱形成的其他二极管共用。

公开(公告)号：US20090309089A1

公开(公告)日：2009-12-17

申请号：US12139435

申请日：2008-06-13

申请人： Kang-Jay Hsia ,  Christopher J. Petti ,  Calvin K. Li

发明人： Kang-Jay Hsia ,  Christopher J. Petti ,  Calvin K. Li

IPC分类号： H01L29/06 ,  H01L29/10 ,  G11C11/00 ,  H01L21/82

CPC分类号： H01L27/1021

摘要： An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

摘要翻译： 提供了一种在导体之间包括垂直取向的二极管结构的集成电路及其制造方法。 诸如无源元件存储单元的两端器件可以包括与反熔丝和/或其他状态改变元件串联的二极管操作元件。 这些装置在上下导体组的交点处使用支柱结构形成。 通过在轨道堆叠中的每个支柱的一个导体上形成二极管的一部分来减小柱结构的高度。 一个实施例中的二极管可以包括第一导电类型的第一二极管部件和第二导电类型的第二二极管部件。 二极管部件之一的一部分被分成第一和第二部分，其中一部分形成在轨道堆叠中，其中与在轨道堆叠处使用柱形成的其他二极管共用。

公开(公告)号：US20090004844A1

公开(公告)日：2009-01-01

申请号：US11771137

申请日：2007-06-29

申请人： Kang-Jay Hsia ,  Calvin K. Li ,  Christopher J. Petti

发明人： Kang-Jay Hsia ,  Calvin K. Li ,  Christopher J. Petti

IPC分类号： H01L21/4763

CPC分类号： H01L21/76838 ,  H01L21/76834 ,  H01L27/1021

摘要： A method is provided to form densely spaced metal lines. A first set of metal lines is formed by etching a first metal layer. A thin dielectric layer is conformally deposited on the first metal lines. A second metal is deposited on the thin dielectric layer, filling gaps between the first metal lines. The second metal layer is planarized to form second metal lines interposed between the first metal lines, coexposing the thin dielectric layer and the second metal layer at a substantially planar surface. In some embodiments, planarization continues to remove the thin dielectric covering tops of the first metal lines, coexposing the first metal lines and the second metal lines, separated by the thin dielectric layer, at a substantially planar surface.

摘要翻译： 提供了一种形成密集间隔的金属线的方法。 通过蚀刻第一金属层形成第一组金属线。 平坦地沉积在第一金属线上的薄介电层。 第二金属沉积在薄介电层上，填充第一金属线之间的间隙。 第二金属层被平坦化以形成插入在第一金属线之间的第二金属线，在基本上平坦的表面处共存薄介电层和第二金属层。 在一些实施例中，平面化继续移除第一金属线的薄电介质覆盖顶部，在基本上平坦的表面处将第一金属线和由薄介电层隔开的第二金属线并入。

公开(公告)号：US20100044756A1

公开(公告)日：2010-02-25

申请号：US12611087

申请日：2009-11-02

申请人： Kang-Jay Hsia ,  Calvin Li ,  Christopher Petti

发明人： Kang-Jay Hsia ,  Calvin Li ,  Christopher Petti

IPC分类号： H01L27/08 ,  H01L21/20

CPC分类号： H01L29/6609 ,  H01L21/76802 ,  H01L27/101 ,  H01L27/1021 ,  H01L29/868

摘要： A method of forming a memory cell is provided, the method including forming a first pillar-shaped element comprising a first semiconductor material, forming a first mold comprising an opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided.

摘要翻译： 提供一种形成存储单元的方法，该方法包括形成包括第一半导体材料的第一柱状元件，形成包括与第一柱状元件自对准的开口的第一模具，以及沉积第二半导体材料 在所述开口中形成在所述第一柱状元件上方的第二柱状元件。 还提供其他方面。

公开(公告)号：US06372520B1

公开(公告)日：2002-04-16

申请号：US09113594

申请日：1998-07-10

申请人： Kang-Jay Hsia ,  George H. Maggard ,  David W. Daniel

发明人： Kang-Jay Hsia ,  George H. Maggard ,  David W. Daniel

IPC分类号： H01L2100

CPC分类号： H01L21/02233 ,  H01L21/02238 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28211 ,  H01L21/3105

摘要： A method and apparatus for repairing and improving the endurance characteristics of process damaged oxide film formed in a semiconductor device involving sonic annealing by vibrating or oscillating a wafer at a predetermined frequency, wave amplitude, and duration. A signal from a frequency generator is amplified by a voltage amplifier and then sent to a speaker or other acoustic device for the production of vibrating acoustical wave energy. This acoustical wave energy is then directed at a submicron device wafer during a specified time period in order to anneal the gate oxide and, thereby, improve the characteristics of the oxide film.

摘要翻译： 一种通过以预定频率，波幅和持续时间振荡或振荡晶片来修复和改善在包括声波退火的半导体器件中形成的工艺损坏氧化膜的耐久性的方法和装置。 来自频率发生器的信号由电压放大器放大，然后发送到扬声器或其他声学装置以产生振动声波能量。 然后将该声波能量在指定的时间段内引导到亚微米器件晶片，以便退火栅极氧化物，从而改善氧化物膜的特性。

公开(公告)号：US07629247B2

公开(公告)日：2009-12-08

申请号：US11786620

申请日：2007-04-12

申请人： Kang-Jay Hsia ,  Calvin Li ,  Christopher Petti

发明人： Kang-Jay Hsia ,  Calvin Li ,  Christopher Petti

IPC分类号： H01L21/4763

CPC分类号： H01L29/6609 ,  H01L21/76802 ,  H01L27/101 ,  H01L27/1021 ,  H01L29/868

摘要： A method of forming a three-dimensional, non-volatile memory array utilizing damascene fabrication techniques is disclosed. A bottom set of conductors is formed and a set of first pillar shaped elements of heavily doped semiconductor material as formed thereon. A mold is formed of insulating material having pillar shaped openings self-aligned with the first pillar shaped elements and a second semiconductor is deposited over the mold to form second pillar shaped elements aligned with the first pillar shaped elements. The pillar elements formed may be further processed by forming another mold of insulating material having trench openings aligned with the pillar shaped elements and then filling the trenches with conductive material to form conductors coupled to the pillar shaped elements.

摘要翻译： 公开了一种使用镶嵌制造技术形成三维非易失性存储阵列的方法。 形成底部的一组导体，并在其上形成一组重掺杂半导体材料的第一柱形元件。 模具由具有与第一柱形元件自对准的柱形开口的绝缘材料形成，并且第二半导体沉积在模具上以形成与第一柱状元件对准的第二柱状元件。 可以通过形成具有与柱状元件对准的沟槽开口的另一个绝缘材料模具，然后用导电材料填充沟槽，以形成连接到柱状元件的导体，来进一步处理所形成的柱元件。

公开(公告)号：US06211051B1

公开(公告)日：2001-04-03

申请号：US09292079

申请日：1999-04-14

申请人： Charles W. Jurgensen ,  Kang-Jay Hsia

发明人： Charles W. Jurgensen ,  Kang-Jay Hsia

IPC分类号： H01L213065

CPC分类号： H01L21/31116 ,  H01L21/76816 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

摘要： A method of fabricating contacts to device elements of an integrated circuit on a semiconductor substrate that includes: (a) using a plasma process to form a first hole in the material above a first portion of the device, wherein the first hole has a depth and a width at the end of the plasma process, and wherein the first hole has an aspect ratio at the end of the plasma process defined by its depth divided by its width; (b) using a plasma process to form a second hole in the material above a second portion of the device, adjacent to the first portion, wherein the second hole has a depth and a width at the end of the plasma process, and wherein the second hole has an aspect ratio at the end of the plasma process defined by its depth divided by its width; and (c) wherein the aspect ratio of the first hole is substantially equivalent to the aspect ratio of the second hole.

摘要翻译： 一种制造与半导体衬底上的集成电路的器件元件的接触的方法，包括：（a）使用等离子体工艺在所述器件的第一部分上方的材料中形成第一孔，其中所述第一孔具有深度和 等离子体处理结束时的宽度，并且其中第一孔具有由其深度除以其宽度限定的等离子体工艺结束时的纵横比; （b）使用等离子体处理在与第一部分相邻的装置的第二部分上方的材料上形成第二孔，其中第二孔在等离子体工艺的结束时具有深度和宽度，并且其中 第二孔在其深度除以其宽度定义的等离子体工艺结束时具有纵横比; 和（c）其中第一孔的纵横比基本上等于第二孔的纵横比。