-
公开(公告)号：US06974991B2
公开(公告)日：2005-12-13
申请号：US10696151
申请日：2003-10-29
申请人： Kangguo Cheng , Ramachandra Divkaruni , Gary Bela Bronner , Carl John Radens , Oleg G. Gluschenkov
发明人： Kangguo Cheng , Ramachandra Divkaruni , Gary Bela Bronner , Carl John Radens , Oleg G. Gluschenkov
IPC分类号： H01L21/8242 , H01L27/108 , H01L31/119
CPC分类号： H01L27/1087 , H01L27/10864 , H01L27/10867
摘要： In a DRAM cell having a trench, a cell capacitor and a cell transistor, a node conducting element connects the cell capacitor to the cell transistor and a collar is disposed about the node conducting element. The collar is disposed in the substrate at least partially, up to entirely outside of the trench. Because the collar is disposed in the substrate outside of the trench, it does not restrict the size of the trench opening. This enables sub-100 nm trenches, using techniques which are compatible with contemporary DRAM process steps. A strap is embedded into a top surface of the collar.
-
2.发明申请公开(公告)号：US20070284640A1
公开(公告)日：2007-12-13
申请号：US11423284
申请日：2006-06-09
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66931
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.
摘要翻译： 半导体结构及其形成方法。 半导体结构包括半导体衬底。 半导体结构还包括在半导体衬底的顶部上的电绝缘区域。 半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。 半导体结构还包括在绝缘区域的顶部上的第二半导体区域。 半导体结构还包括在第一半导体区域和半导体衬底中的电容器。 半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。
-
3.发明申请METHODS OF FABRICATING P-I-N DIODES, STRUCTURES FOR P-I-N DIODES AND DESIGN STRUCTURE FOR P-I-N DIODES 有权制备P-I-N二极体的方法，P-I-N二极体的结构和P-I-N二极体的设计结构公开(公告)号：US20100173449A1
公开(公告)日：2010-07-08
申请号：US12349018
申请日：2009-01-06
CPC分类号： H01L29/868 , H01L29/6609
摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
摘要翻译： 制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。 一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。
-
公开(公告)号：US20070284612A1
公开(公告)日：2007-12-13
申请号：US11423280
申请日：2006-06-09
IPC分类号： H01L31/00
CPC分类号： H01L29/66181 , H01L27/10867
摘要： Structures and methods for forming the same. A semiconductor fabrication method comprises a step of providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate and a capacitor electrode on the semiconductor substrate. The capacitor electrode comprises dopants, and is electrically insulated from the semiconductor substrate by a capacitor dielectric layer. The semiconductor structure further includes a semiconductor layer on the semiconductor substrate. The semiconductor layer comprises a trench which partially but not completely overlaps the capacitor electrode. The method further comprises the step of causing some of the dopants of the capacitor electrode to diffuse into the semiconductor layer, resulting in a doped source/drain region. The doped source/drain region overlaps the capacitor electrode and abuts a sidewall of the trench.
摘要翻译： 用于形成它的结构和方法。 半导体制造方法包括提供半导体结构的步骤。 半导体结构包括在半导体衬底上的半导体衬底和电容器电极。 电容器电极包括掺杂剂，并且通过电容器介电层与半导体衬底电绝缘。 半导体结构还包括半导体衬底上的半导体层。 半导体层包括与电容器电极部分但不完全重叠的沟槽。 该方法还包括使电容器电极的一些掺杂剂扩散到半导体层中的步骤，产生掺杂的源极/漏极区域。 掺杂源极/漏极区域与电容器电极重叠并邻接沟槽的侧壁。
-
5.发明授权公开(公告)号：US07569450B2
公开(公告)日：2009-08-04
申请号：US11423284
申请日：2006-06-09
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L29/66931
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.
摘要翻译： 半导体结构及其形成方法。 半导体结构包括半导体衬底。 半导体结构还包括在半导体衬底的顶部上的电绝缘区域。 半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。 半导体结构还包括在绝缘区域的顶部上的第二半导体区域。 半导体结构还包括在第一半导体区域和半导体衬底中的电容器。 半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。
-
6.发明授权Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes 有权制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构公开(公告)号：US07919347B2
公开(公告)日：2011-04-05
申请号：US12349018
申请日：2009-01-06
IPC分类号： H01L29/868
CPC分类号： H01L29/868 , H01L29/6609
摘要： Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes. A method includes: forming a trench in a silicon substrate; forming a doped region in the substrate abutting the trench; growing an intrinsic epitaxial silicon layer on surfaces of the trench; depositing a doped polysilicon layer to fill remaining space in the trench, performing a chemical mechanical polish so top surfaces of the intrinsic epitaxial silicon layer and the doped polysilicon layer are coplanar; forming a dielectric isolation layer in the substrate; forming a dielectric layer on top of the isolation layer; and forming a first metal contact to the doped polysilicon layer through the dielectric layer and a second contact to the doped region the dielectric and through the isolation layer.
摘要翻译： 制造P-I-N二极管的方法，P-I-N二极管的结构和P-I-N二极管的设计结构。 一种方法包括：在硅衬底中形成沟槽; 在所述衬底中形成邻接所述沟槽的掺杂区域; 在沟槽的表面上生长本征的外延硅层; 沉积掺杂多晶硅层以填充沟槽中的剩余空间，执行化学机械抛光，使得本征外延硅层和掺杂多晶硅层的顶表面是共面的; 在衬底中形成绝缘隔离层; 在隔离层的顶部形成介电层; 以及通过介电层形成第一金属接触到掺杂多晶硅层，以及通过第二接触到掺杂区域介电层并通过隔离层。
-
公开(公告)号：US08535970B2
公开(公告)日：2013-09-17
申请号：US13154140
申请日：2011-06-06
申请人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
发明人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
IPC分类号： H01L21/00
CPC分类号： H01L31/1804 , H01L31/02167 , H01L31/022425 , H01L31/068 , Y02E10/547 , Y02P70/521
摘要： The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.
摘要翻译： 本发明涉及一种光伏太阳能电池（100）的制造方法，包括：在光伏太阳能电池（100）的后侧（18）上提供高掺杂区域（20），提供位于所述光伏太阳能电池（100）上的局部金属触点（30） 提供覆盖所述触头（30）之间的表面（52）的钝化层（50），其中触点（30）保持基本上不含钝化层（50），并沉积金属层（50） 32）用于背面场。
-
8.发明授权Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors 失效增强的绝缘体上硅（SOI）晶体管和制造增强型SOI晶体管的方法公开(公告)号：US07250351B2
公开(公告)日：2007-07-31
申请号：US11106002
申请日：2005-04-14
IPC分类号： H01L29/76
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译： 提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。 增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。 在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。
-
9.发明授权Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact 有权制造具有垂直器件阵列和边界位线接触的嵌入式DRAM的结构和方法公开(公告)号：US06727540B2
公开(公告)日：2004-04-27
申请号：US10227404
申请日：2002-08-23
IPC分类号： H01L27108
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10864
摘要： An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.
摘要翻译： 本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体 沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元进一步包括从晶体管沟道延伸的有源区和与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。
-
10.发明授权Method of simultaneously forming a line interconnect and a borderless contact to diffusion 失效同时形成线路互连和无边界接触到扩散的方法公开(公告)号：US06245651B1
公开(公告)日：2001-06-12
申请号：US09481916
申请日：2000-01-12
IPC分类号： H01L213205
CPC分类号： H01L27/10894 , H01L21/76802 , H01L27/10888
摘要： A method for simultaneously forming a line interconnect such as a bitline and a borderless contact to diffusion, e.g. bitline contact, is described. A semiconductor substrate having prepatterned gate stacks thereon is covered with a first dielectric to form a first level and then a second dielectric is deposited which forms a second level. Line interconnect openings are defined in the second level by lithography and etching. Etching is continued down to monocrystalline regions in an array region of the substrate to form borderless contact openings coincident to the line interconnects between the gate stacks. The openings are filled with one or more conductors to form contacts to diffusion, e.g. bitline contacts, which are coincident to the line interconnects, e.g. bitlines.
摘要翻译： 用于同时形成诸如位线和无边界接触之类的线互连的扩散的方法，例如。 描述了位线接触。 其上具有形成图案化栅极堆叠的半导体衬底被第一电介质覆盖以形成第一电平，然后沉积形成第二电平的第二电介质。 线路互连开口通过光刻和蚀刻在第二层限定。 在衬底的阵列区域中继续蚀刻到单晶区域以形成与栅叠层之间的线互连一致的无边界接触开口。 开口填充有一个或多个导体以形成扩散接触，例如。 位线接触，其与线互连一致，例如。 位线
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.027 秒)
