Doped polysilicon to retard boron diffusion into and through thin gate
dielectrics
    2.
    发明授权
    Doped polysilicon to retard boron diffusion into and through thin gate dielectrics 失效
    掺杂的多晶硅以阻止硼扩散进入并通过薄栅极电介质

    公开(公告)号:US6030874A

    公开(公告)日:2000-02-29

    申请号:US7060

    申请日:1998-01-13

    摘要: An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.

    摘要翻译: 本发明的实施例是一种制造半导体器件的方法,该半导体器件包括位于导电结构和半导体衬底之间的电介质层,该方法包括以下步骤:在半导体衬底(衬底)上形成介电层(层14) 12); 在电介质层上形成导电结构(结构18); 用硼掺杂导电结构; 并用抑制硼扩散的掺杂​​剂掺杂导电结构。 半导体器件可以是PMOS晶体管或电容器。 优选地,导电结构是栅极结构。 电介质层优选由选自氧化物,氧化物/氧化物堆,氧化物/氮化物叠层和氧氮化物的材料组成。 优选地,抑制硼扩散的掺杂​​剂包含至少一个III族或IV族元素。 更具体地,其优选包括:碳,锗及其任何组合。 优选地,用硼掺杂导电结构并用抑制硼的扩散的掺杂​​剂掺杂导电结构的步骤基本上同时实现,或者在掺杂导电的步骤之前预先形成用硼掺杂导电结构的步骤 具有抑制硼扩散的掺杂​​剂的结构基本上同时完成。

    Process for monitoring the thickness of layers in a microelectronic device

    公开(公告)号:US06605482B2

    公开(公告)日:2003-08-12

    申请号:US09975637

    申请日:2001-10-11

    IPC分类号: H01L2166

    CPC分类号: G01N21/55

    摘要: A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device. The method additionally includes comparing the at least one optical measurement to the predicted behavior curve and determining the approximate actual depth of the interface in response to the compared optical measurement.