公开(公告)号：US20120044776A1

公开(公告)日：2012-02-23

申请号：US13213913

申请日：2011-08-19

申请人： Katsuhiro KITAGAWA ,  Shotaro KOBAYASHI

发明人： Katsuhiro KITAGAWA ,  Shotaro KOBAYASHI

IPC分类号： G11C7/00 ,  H03L7/06 ,  H03L7/00

CPC分类号： G11C11/4076 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4093 ,  H03L7/0812

摘要： A semiconductor device comprises: a control signal generating circuit that generates and outputs a control signal that is in an active state during a period around at least one of rising edges and falling edges of a clock signal; and a data input circuit that is controlled to be in an active state, in which a data signal can be received, while the control signal is in an active state, and otherwise controlled to be in an inactive state.

摘要翻译： 一种半导体器件，包括：控制信号产生电路，其在周期中围绕时钟信号的上升沿和下降沿中的至少一个周期产生并输出处于有效状态的控制信号; 以及控制在处于活动状态的数据输入电路，其中可以接收数据信号，同时控制信号处于活动状态，否则控制为处于非活动状态。

公开(公告)号：US20100231275A1

公开(公告)日：2010-09-16

申请号：US12724011

申请日：2010-03-15

申请人： Katsuhiro KITAGAWA

发明人： Katsuhiro KITAGAWA

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： G11C7/222 ,  G11C5/063 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C2207/2254 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the CDT operation in which strict phase control is not required can be reduced.

摘要翻译： 半导体器件包括具有ODT功能的数据输入/输出电路和产生用于确定数据输入/输出电路的操作定时的内部时钟的DLL电路。 DLL电路具有用于以精确的方式控制内部时钟的相位的第一模式和用于以低功耗操作的第二模式。 当数据输入/输出电路不执行ODT操作时，DLL电路以第一模式工作，并且当数据输入/输出电路执行ODT操作时，DLL电路以第二模式工作。 以这种方式，根据ODT操作切换DLL电路的操作模式，从而可以减少不需要严格相位控制的CDT操作中的功耗。

公开(公告)号：US20110022808A1

公开(公告)日：2011-01-27

申请号：US12836201

申请日：2010-07-14

申请人： Katsuhiro KITAGAWA ,  Hiroshi ICHIKAWA

发明人： Katsuhiro KITAGAWA ,  Hiroshi ICHIKAWA

IPC分类号： G06F12/00 ,  G11C7/00 ,  H03B1/00

CPC分类号： G11C11/4093 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1069 ,  G11C7/1072

摘要： An output driver has a first driver connected between a first power source and an output terminal and a second driver connected between a second power source and the output terminal. One of the first driver and the second driver has two driving parts connected in parallel to each other. The two driving parts and the other of the first driver and the second driver are operated by independent input signals.

摘要翻译： 输出驱动器具有连接在第一电源和输出端之间的第一驱动器和连接在第二电源和输出端之间的第二驱动器。 第一驱动器和第二驱动器之一具有彼此并联连接的两个驱动部件。 第一驱动器和第二驱动器中的两个驱动部分和另一个驱动器由独立的输入信号操作。

公开(公告)号：US20140177361A1

公开(公告)日：2014-06-26

申请号：US14193345

申请日：2014-02-28

申请人： Katsuhiro KITAGAWA

发明人： Katsuhiro KITAGAWA

IPC分类号： G11C7/22

CPC分类号： G11C7/222 ,  G11C5/063 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C2207/2254 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.

摘要翻译： 半导体器件包括具有ODT功能的数据输入/输出电路和产生用于确定数据输入/输出电路的操作定时的内部时钟的DLL电路。 DLL电路具有用于以精确的方式控制内部时钟的相位的第一模式和用于以低功耗操作的第二模式。 当数据输入/输出电路不执行ODT操作时，DLL电路以第一模式工作，并且当数据输入/输出电路执行ODT操作时，DLL电路以第二模式工作。 以这种方式，根据ODT操作来切换DLL电路的操作模式，从而可以减少不需要严格相位控制的ODT操作中的功耗。

公开(公告)号：US20140167826A1

公开(公告)日：2014-06-19

申请号：US14188123

申请日：2014-02-24

申请人： Katsuhiro KITAGAWA

发明人： Katsuhiro KITAGAWA

IPC分类号： H03L7/185

CPC分类号： H03L7/185 ,  H03K5/131 ,  H03K5/133 ,  H03L7/0814

摘要： Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output, an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.

摘要翻译： 本文公开了一种包括在输入节点和输出节点之间串联连接的多个单触发脉冲发生电路的装置。 单触发脉冲发生电路中的每一个接收从先前连接的单触发脉冲发生电路提供的输入时钟信号，输出输出时钟信号到随后连接的单触发脉冲发生电路。 基于输入时钟信号的上升沿和下降沿之一来控制输出时钟信号的上升沿和下降沿。 从输出时钟信号的上升沿和下降沿之一到输出时钟信号的上升沿和下降沿中的另一个的时间段是可变的。

公开(公告)号：US20130043919A1

公开(公告)日：2013-02-21

申请号：US13585110

申请日：2012-08-14

申请人： Katsuhiro KITAGAWA

发明人： Katsuhiro KITAGAWA

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/185 ,  H03K5/131 ,  H03K5/133 ,  H03L7/0814

摘要： Disclosed herein is a device that includes a plurality of one-shot pulse generation circuits connected in series between an input node and an output node. Each of the one-shot pulse generation circuits receives an input clock signal supplied from previously connected one-shot pulse generation circuit to output an output clock signal to subsequently connected one-shot pulse generation circuit. Both of a rising edge and a falling edge of the output clock signal are controlled based on one of a rising edge and a falling edge of the input clock signal. A time period from one of the rising edge and the falling edge of the output clock signal to the other of the rising edge and the falling edge of the output clock signal being variable.

摘要翻译： 本文公开了一种包括在输入节点和输出节点之间串联连接的多个单触发脉冲发生电路的装置。 每个单触发脉冲发生电路接收从先前连接的单触发脉冲发生电路提供的输入时钟信号，以将输出时钟信号输出到随后连接的单触发脉冲发生电路。 基于输入时钟信号的上升沿和下降沿之一来控制输出时钟信号的上升沿和下降沿。 从输出时钟信号的上升沿和下降沿之一到输出时钟信号的上升沿和下降沿的另一个的时间段是可变的。