公开(公告)号：US08569839B2

公开(公告)日：2013-10-29

申请号：US13010417

申请日：2011-01-20

申请人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

发明人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

IPC分类号： H01L21/8238 ,  H01L21/70

CPC分类号： H01L21/76283 ,  H01L21/76232 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

摘要翻译： 提供可以使用简单的工艺制造而不确保高嵌入性的半导体器件; 以及该装置的制造方法。 在根据本发明的半导体器件的制造方法中，首先准备具有通过堆叠支撑衬底，埋入绝缘膜和半导体层获得的构造的半导体衬底。 然后，在半导体层的主表面上完成具有导电部分的元件。 形成了在平面图中包围元件并从半导体层的主表面到达掩埋绝缘膜的沟槽。 在元件上和沟槽中形成第一绝缘膜（层间绝缘膜）以覆盖元件并分别在沟槽中形成气隙。 然后，在第一绝缘膜中形成到达元件的导电部分的接触孔。

公开(公告)号：US20110062547A1

公开(公告)日：2011-03-17

申请号：US12882863

申请日：2010-09-15

申请人： Kazuma ONISHI ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

发明人： Kazuma ONISHI ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

IPC分类号： H01L29/02 ,  H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

摘要翻译： 一种半导体器件，其通过简单的工艺消除了对高填充性的需要及其制造方法。 在半导体衬底的表面上完成包括源极区和漏极区的高击穿电压横向MOS晶体管。 在半导体衬底的表面中制造在平面图中观察时围绕晶体管的沟槽。 在晶体管和沟槽中形成绝缘膜，以覆盖晶体管并在沟槽中形成气隙空间。 到达晶体管的源极区域和漏极区域的接触孔分别制成层间绝缘膜。

公开(公告)号：US08357989B2

公开(公告)日：2013-01-22

申请号：US12882863

申请日：2010-09-15

申请人： Kazuma Onishi ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

发明人： Kazuma Onishi ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

摘要翻译： 一种半导体器件，其通过简单的工艺消除了对高填充性的需要及其制造方法。 在半导体基板的表面上完成包括源极区域和漏极区域的高耐压侧的横向MOS晶体管。 在半导体衬底的表面中制造在平面图中观察时围绕晶体管的沟槽。 在晶体管和沟槽中形成绝缘膜，以覆盖晶体管并在沟槽中形成气隙空间。 到达晶体管的源极区域和漏极区域的接触孔分别制成层间绝缘膜。

公开(公告)号：US20100181640A1

公开(公告)日：2010-07-22

申请号：US12690714

申请日：2010-01-20

申请人： Tatsuya SHIROMOTO ,  Tetsuya Nitta ,  Shigeo Tokumitsu

发明人： Tatsuya SHIROMOTO ,  Tetsuya Nitta ,  Shigeo Tokumitsu

IPC分类号： H01L29/06

CPC分类号： H01L21/76264

摘要： Provided is a semiconductor device about which the reliability thereof is certainly kept even when a void is generated in a buried film in its trench. A rectangular element formation region is formed in a silicon layer. A trench having a predetermined width is formed to surround the element formation region. A first TEOS film and a second TEOS film are buried in the trench. A protecting film is formed at an L-shaped intersection region of the trench.

摘要翻译： 提供一种半导体器件，即使在其沟槽中的掩埋膜中产生空隙时，其可靠性肯定保持不变。 在硅层中形成矩形元件形成区域。 形成具有预定宽度的沟槽以包围元件形成区域。 第一TEOS膜和第二TEOS膜被埋在沟槽中。 保护膜形成在沟槽的L形交叉区域。

公开(公告)号：US20120049318A1

公开(公告)日：2012-03-01

申请号：US13208273

申请日：2011-08-11

申请人： Tatsuya Kawamata ,  Atsushi Tachigami ,  Kazuya Horie ,  Tatsuya Shiromoto ,  Tetsuya Nitta ,  Hironori Shimizu

发明人： Tatsuya Kawamata ,  Atsushi Tachigami ,  Kazuya Horie ,  Tatsuya Shiromoto ,  Tetsuya Nitta ,  Hironori Shimizu

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76283 ,  H01L21/3065 ,  H01L21/76232 ,  H01L29/7833

摘要： To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 μm. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.

摘要翻译： 为了在元件隔离的元件区域的外围设置在SOI衬底上形成的SOI衬底的半导体层的半导体器件中，能够防止因元件隔离引起的可靠性劣化的技术。 通过将深沟槽构造沟槽隔离的上部的沟槽宽度设定为小于1.2，可以防止从绝缘膜的上表面填充具有绝缘膜的深沟槽形成的中空部的外观 μm。 可以通过在深沟槽的上部形成连接到深沟槽的上部的LOCOS绝缘膜来防止由于深沟槽的上部的沟槽宽度的减小而可能发生的相邻元件区域之间的击穿电压的降低 绝缘膜填充在深沟槽中。

公开(公告)号：US08710619B2

公开(公告)日：2014-04-29

申请号：US13208273

申请日：2011-08-11

申请人： Tatsuya Kawamata ,  Atsushi Tachigami ,  Kazuya Horie ,  Tatsuya Shiromoto ,  Tetsuya Nitta ,  Hironori Shimizu

发明人： Tatsuya Kawamata ,  Atsushi Tachigami ,  Kazuya Horie ,  Tatsuya Shiromoto ,  Tetsuya Nitta ,  Hironori Shimizu

IPC分类号： H01L21/70

CPC分类号： H01L21/76283 ,  H01L21/3065 ,  H01L21/76232 ,  H01L29/7833

摘要： To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 μm. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.

摘要翻译： 为了在元件隔离的元件区域的外围设置在SOI衬底上形成的SOI衬底的半导体层的半导体器件中，能够防止因元件隔离引起的可靠性劣化的技术。 通过将深沟槽构造沟槽隔离的上部的沟槽宽度设定为小于1.2，可以防止从绝缘膜的上表面填充具有绝缘膜的深沟槽形成的中空部的外观 μm。 可以通过在深沟槽的上部形成连接到深沟槽的上部的LOCOS绝缘膜来防止由于深沟槽的上部的沟槽宽度的减小而可能发生的相邻元件区域之间的击穿电压的降低 绝缘膜填充在深沟槽中。

公开(公告)号：US08344458B2

公开(公告)日：2013-01-01

申请号：US13110630

申请日：2011-05-18

申请人： Yasuki Yoshihisa ,  Kikuo Kato ,  Tetsuya Nitta ,  Kazuma Onishi

发明人： Yasuki Yoshihisa ,  Kikuo Kato ,  Tetsuya Nitta ,  Kazuma Onishi

IPC分类号： H01L23/62

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/0251 ,  H01L27/088

摘要： There is provided a semiconductor device capable of suppressing malfunction of an element to be protected, caused by electrons from an output element into a semiconductor substrate. The semiconductor device is provided with the semiconductor substrate, the output element, the element to be protected, a tap part, and a first active-barrier structure. The first active-barrier structure is disposed between the element to be protected and the tap part. Further, the first active-barrier structure includes an n-type region joined with a p-type doped region, and a p-type region in ohmic coupling with the n-type region.

摘要翻译： 提供一种半导体器件，其能够抑制从输出元件到半导体衬底的电子引起的被保护元件的故障。 半导体器件设置有半导体衬底，输出元件，要保护的元件，抽头部件和第一有源屏障结构。 第一主动阻挡结构设置在待保护元件与抽头部件之间。 此外，第一有源屏障结构包括与p型掺杂区域连接的n型区域和与n型区域欧姆耦合的p型区域。

公开(公告)号：US07418889B2

公开(公告)日：2008-09-02

申请号：US10913547

申请日：2004-08-09

申请人： Tetsuya Nitta

发明人： Tetsuya Nitta

IPC分类号： B23Q16/10

CPC分类号： B23Q1/28 ,  B23Q16/102 ,  Y10T74/14 ,  Y10T74/1494

摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.

公开(公告)号：US20080148901A1

公开(公告)日：2008-06-26

申请号：US12068933

申请日：2008-02-13

申请人： Tetsuya Nitta

发明人： Tetsuya Nitta

IPC分类号： B23Q16/10

CPC分类号： B23Q1/28 ,  B23Q16/102 ,  Y10T74/14 ,  Y10T74/1494

摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.

摘要翻译： 分度台组件包括旋转台，沿旋转台的旋转轴线的方向与旋转台分离的框架，用于通过沿旋转轴线移动旋转台来使旋转台与框架接触的夹紧装置 设置在所述转台和所述框架之间的第一轴承以及设置在所述第一轴承与所述旋转台和所述框架中的一个之间的推动装置，并且至少在所述旋转台和所述框架中将所述第一轴承压靠在所述旋转台和所述框架中的另一个上时 旋转台旋转。

公开(公告)号：US07339236B2

公开(公告)日：2008-03-04

申请号：US11352344

申请日：2006-02-13

申请人： Tetsuya Nitta ,  Yasunori Yamashita ,  Shinichiro Yanagi ,  Fumitoshi Yamamoto

发明人： Tetsuya Nitta ,  Yasunori Yamashita ,  Shinichiro Yanagi ,  Fumitoshi Yamamoto

IPC分类号： H01L27/01 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/78606 ,  H01L21/84 ,  H01L27/12 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78624

摘要： The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

摘要翻译： 本发明提供一种半导体技术，能够抑制晶体管的阈值电压的增加，并且还提高源极区域和漏极区域之间的耐受电压。 在SOI衬底中的n + O型半导体层中形成p沟道型MOS晶体管的源极和漏极区域。 此外，在半导体层中形成n型杂质区。 杂质区域形成在源极区域的正下方的源极区域的整个底部上，并且也形成在源极区域和漏极区域之间的半导体层的正下方。 将杂质区域中的杂质浓度的峰值位置设定在源极区域和源极区域之间的半导体层的正上方的正下方的源极区域的最下端。