公开(公告)号：US08569839B2

公开(公告)日：2013-10-29

申请号：US13010417

申请日：2011-01-20

申请人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

发明人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

IPC分类号： H01L21/8238 ,  H01L21/70

CPC分类号： H01L21/76283 ,  H01L21/76232 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

摘要翻译： 提供可以使用简单的工艺制造而不确保高嵌入性的半导体器件; 以及该装置的制造方法。 在根据本发明的半导体器件的制造方法中，首先准备具有通过堆叠支撑衬底，埋入绝缘膜和半导体层获得的构造的半导体衬底。 然后，在半导体层的主表面上完成具有导电部分的元件。 形成了在平面图中包围元件并从半导体层的主表面到达掩埋绝缘膜的沟槽。 在元件上和沟槽中形成第一绝缘膜（层间绝缘膜）以覆盖元件并分别在沟槽中形成气隙。 然后，在第一绝缘膜中形成到达元件的导电部分的接触孔。

公开(公告)号：US20100181640A1

公开(公告)日：2010-07-22

申请号：US12690714

申请日：2010-01-20

申请人： Tatsuya SHIROMOTO ,  Tetsuya Nitta ,  Shigeo Tokumitsu

发明人： Tatsuya SHIROMOTO ,  Tetsuya Nitta ,  Shigeo Tokumitsu

IPC分类号： H01L29/06

CPC分类号： H01L21/76264

摘要： Provided is a semiconductor device about which the reliability thereof is certainly kept even when a void is generated in a buried film in its trench. A rectangular element formation region is formed in a silicon layer. A trench having a predetermined width is formed to surround the element formation region. A first TEOS film and a second TEOS film are buried in the trench. A protecting film is formed at an L-shaped intersection region of the trench.

摘要翻译： 提供一种半导体器件，即使在其沟槽中的掩埋膜中产生空隙时，其可靠性肯定保持不变。 在硅层中形成矩形元件形成区域。 形成具有预定宽度的沟槽以包围元件形成区域。 第一TEOS膜和第二TEOS膜被埋在沟槽中。 保护膜形成在沟槽的L形交叉区域。

公开(公告)号：US09064689B2

公开(公告)日：2015-06-23

申请号：US13451145

申请日：2012-04-19

申请人： Shigeo Tokumitsu ,  Akio Uenishi

发明人： Shigeo Tokumitsu ,  Akio Uenishi

IPC分类号： H01L29/10 ,  H01L21/38 ,  H01L29/78 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/1045 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0207 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/4238 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7836

摘要： The high voltage transistor includes a first impurity layer, a second impurity layer formed inside the first impurity layer, so as to put the second impurity layer between them, a pair of third impurity layers and fourth impurity layers formed inside the first impurity layer, a fifth impurity layer formed from the uppermost surface of the first impurity layer to the inside of the first impurity layer so as to protrude along the main surface in the direction where the second impurity layer is disposed, and a conductive layer formed above the uppermost surface of the second impurity layer. The concentration of the impurity in the fourth impurity layer is higher than the concentration of the impurity in the third and the fifth impurity layers, and the concentration of the impurity in the fifth impurity layer is higher than the concentration of the impurity in the third impurity layer.

摘要翻译： 高压晶体管包括第一杂质层，形成在第一杂质层内的第二杂质层，以将第二杂质层置于它们之间，形成在第一杂质层内部的一对第三杂质层和第四杂质层， 第五杂质层从第一杂质层的最上表面到第一杂质层的内部沿着主表面沿着第二杂质层的方向突出，并且形成在第一杂质层的最上表面上方的导电层 第二杂质层。 第四杂质层中的杂质浓度高于第三和第五杂质层中的杂质浓度，第五杂质层中的杂质浓度高于第三杂质中的杂质浓度 层。

公开(公告)号：US07136301B2

公开(公告)日：2006-11-14

申请号：US10956124

申请日：2004-10-04

申请人： Shigeo Tokumitsu

发明人： Shigeo Tokumitsu

IPC分类号： G11C5/06 ,  G11C11/40 ,  H01L29/792

CPC分类号： H01L29/513 ,  G11C16/0475 ,  H01L29/518 ,  H01L29/7923

摘要： First active regions and second active regions intersecting the first active regions at a right angle are defined on the surface of a semiconductor substrate, and diffusion regions are formed in the first and second active regions to interpose an intersecting region therebetween. Then, a gate structure is formed linearly to extend over the intersecting region at a non-zero angle with respect to the first and second active regions. Further, terminals to be connected to metal interconnects are provided on the diffusion regions at a non-zero angle with respect to the first and second active regions, respectively. Consequently provided is a nonvolatile semiconductor memory having a simple gate structure capable of storing 4-bits of information in one memory cell.

摘要翻译： 在半导体衬底的表面上限定与第一有源区域成直角相交的第一有源区和第二有源区，并且在第一和第二有源区中形成扩散区以在其间插入相交区域。 然后，栅极结构线性形成，以相对于第一和第二有源区域以非零角度在交叉区域上延伸。 此外，要连接到金属互连的端子分别相对于第一和第二有源区域以非零角度设置在扩散区域上。 因此，提供了一种具有能够在一个存储单元中存储4位信息的简单门结构的非易失性半导体存储器。

公开(公告)号：US20050073002A1

公开(公告)日：2005-04-07

申请号：US10956124

申请日：2004-10-04

申请人： Shigeo Tokumitsu

发明人： Shigeo Tokumitsu

IPC分类号： G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/513 ,  G11C16/0475 ,  H01L29/518 ,  H01L29/7923

摘要： First active regions and second active regions intersecting the first active regions at a right angle are defined on the surface of a semiconductor substrate, and diffusion regions are formed in the first and second active regions to interpose an intersecting region therebetween. Then, a gate structure is formed linearly to extend over the intersecting region. Further, terminals to be connected to metal interconnects are provided on the diffusion regions, respectively. Consequently provided is a nonvolatile semiconductor memory having a simple gate structure capable of storing 4-bits of information in one memory cell.

摘要翻译： 在半导体衬底的表面上限定与第一有源区域成直角相交的第一有源区和第二有源区，并且在第一和第二有源区中形成扩散区以在其间插入相交区域。 然后，栅极结构线性地形成以在交叉区域上延伸。 此外，分别在扩散区域上设置要连接到金属互连的端子。 因此，提供了一种具有能够在一个存储单元中存储4位信息的简单门结构的非易失性半导体存储器。