公开(公告)号：US20110062547A1

公开(公告)日：2011-03-17

申请号：US12882863

申请日：2010-09-15

申请人： Kazuma ONISHI ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

发明人： Kazuma ONISHI ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

IPC分类号： H01L29/02 ,  H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

摘要翻译： 一种半导体器件，其通过简单的工艺消除了对高填充性的需要及其制造方法。 在半导体衬底的表面上完成包括源极区和漏极区的高击穿电压横向MOS晶体管。 在半导体衬底的表面中制造在平面图中观察时围绕晶体管的沟槽。 在晶体管和沟槽中形成绝缘膜，以覆盖晶体管并在沟槽中形成气隙空间。 到达晶体管的源极区域和漏极区域的接触孔分别制成层间绝缘膜。

公开(公告)号：US08357989B2

公开(公告)日：2013-01-22

申请号：US12882863

申请日：2010-09-15

申请人： Kazuma Onishi ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

发明人： Kazuma Onishi ,  Yoshitaka Otsu ,  Hiroshi Kimura ,  Tetsuya Nitta ,  Shinichiro Yanagi ,  Katsumi Morii

IPC分类号： H01L29/00 ,  H01L21/76

CPC分类号： H01L29/0649 ,  H01L21/764 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0922 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film.

摘要翻译： 一种半导体器件，其通过简单的工艺消除了对高填充性的需要及其制造方法。 在半导体基板的表面上完成包括源极区域和漏极区域的高耐压侧的横向MOS晶体管。 在半导体衬底的表面中制造在平面图中观察时围绕晶体管的沟槽。 在晶体管和沟槽中形成绝缘膜，以覆盖晶体管并在沟槽中形成气隙空间。 到达晶体管的源极区域和漏极区域的接触孔分别制成层间绝缘膜。

公开(公告)号：US08569839B2

公开(公告)日：2013-10-29

申请号：US13010417

申请日：2011-01-20

申请人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

发明人： Katsumi Morii ,  Yoshitaka Otsu ,  Kazuma Onishi ,  Tetsuya Nitta ,  Tatsuya Shiromoto ,  Shigeo Tokumitsu

IPC分类号： H01L21/8238 ,  H01L21/70

CPC分类号： H01L21/76283 ,  H01L21/76232 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

摘要翻译： 提供可以使用简单的工艺制造而不确保高嵌入性的半导体器件; 以及该装置的制造方法。 在根据本发明的半导体器件的制造方法中，首先准备具有通过堆叠支撑衬底，埋入绝缘膜和半导体层获得的构造的半导体衬底。 然后，在半导体层的主表面上完成具有导电部分的元件。 形成了在平面图中包围元件并从半导体层的主表面到达掩埋绝缘膜的沟槽。 在元件上和沟槽中形成第一绝缘膜（层间绝缘膜）以覆盖元件并分别在沟槽中形成气隙。 然后，在第一绝缘膜中形成到达元件的导电部分的接触孔。

公开(公告)号：US07339236B2

公开(公告)日：2008-03-04

申请号：US11352344

申请日：2006-02-13

申请人： Tetsuya Nitta ,  Yasunori Yamashita ,  Shinichiro Yanagi ,  Fumitoshi Yamamoto

发明人： Tetsuya Nitta ,  Yasunori Yamashita ,  Shinichiro Yanagi ,  Fumitoshi Yamamoto

IPC分类号： H01L27/01 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/78606 ,  H01L21/84 ,  H01L27/12 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78624

摘要： The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

摘要翻译： 本发明提供一种半导体技术，能够抑制晶体管的阈值电压的增加，并且还提高源极区域和漏极区域之间的耐受电压。 在SOI衬底中的n + O型半导体层中形成p沟道型MOS晶体管的源极和漏极区域。 此外，在半导体层中形成n型杂质区。 杂质区域形成在源极区域的正下方的源极区域的整个底部上，并且也形成在源极区域和漏极区域之间的半导体层的正下方。 将杂质区域中的杂质浓度的峰值位置设定在源极区域和源极区域之间的半导体层的正上方的正下方的源极区域的最下端。

公开(公告)号：US08344458B2

公开(公告)日：2013-01-01

申请号：US13110630

申请日：2011-05-18

申请人： Yasuki Yoshihisa ,  Kikuo Kato ,  Tetsuya Nitta ,  Kazuma Onishi

发明人： Yasuki Yoshihisa ,  Kikuo Kato ,  Tetsuya Nitta ,  Kazuma Onishi

IPC分类号： H01L23/62

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/0251 ,  H01L27/088

摘要： There is provided a semiconductor device capable of suppressing malfunction of an element to be protected, caused by electrons from an output element into a semiconductor substrate. The semiconductor device is provided with the semiconductor substrate, the output element, the element to be protected, a tap part, and a first active-barrier structure. The first active-barrier structure is disposed between the element to be protected and the tap part. Further, the first active-barrier structure includes an n-type region joined with a p-type doped region, and a p-type region in ohmic coupling with the n-type region.

摘要翻译： 提供一种半导体器件，其能够抑制从输出元件到半导体衬底的电子引起的被保护元件的故障。 半导体器件设置有半导体衬底，输出元件，要保护的元件，抽头部件和第一有源屏障结构。 第一主动阻挡结构设置在待保护元件与抽头部件之间。 此外，第一有源屏障结构包括与p型掺杂区域连接的n型区域和与n型区域欧姆耦合的p型区域。

公开(公告)号：US20060180862A1

公开(公告)日：2006-08-17

申请号：US11352344

申请日：2006-02-13

申请人： Tetsuya Nitta ,  Yasunori Yamashita ,  Shinichiro Yanagi ,  Fumitoshi Yamamoto

发明人： Tetsuya Nitta ,  Yasunori Yamashita ,  Shinichiro Yanagi ,  Fumitoshi Yamamoto

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/78606 ,  H01L21/84 ,  H01L27/12 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/78624

摘要： The present invention provides a semiconductor technology capable of suppressing an increase in threshold voltage of a transistor and, also, improving a withstand voltage between a source region and a drain region. Source and drain regions of a p channel type MOS transistor are formed in an n− type semiconductor layer in an SOI substrate. In addition, an n type impurity region is formed in the semiconductor layer. The impurity region is formed over the entire bottom of the source region at a portion directly below this source region, and is also formed directly below the semiconductor layer between the source region and the drain region. A peak position of an impurity concentration in the impurity region is set below a lowest end of the source region at a portion directly below an upper surface of the semiconductor layer between the source region and the drain region.

摘要翻译： 本发明提供一种半导体技术，能够抑制晶体管的阈值电压的增加，并且还提高源极区域和漏极区域之间的耐受电压。 在SOI衬底中的n + O型半导体层中形成p沟道型MOS晶体管的源极和漏极区域。 此外，在半导体层中形成n型杂质区。 杂质区域形成在源极区域的正下方的源极区域的整个底部上，并且也形成在源极区域和漏极区域之间的半导体层的正下方。 将杂质区域中的杂质浓度的峰值位置设定在源极区域和源极区域之间的半导体层的正上方的正下方的源极区域的最下端。

公开(公告)号：US07418889B2

公开(公告)日：2008-09-02

申请号：US10913547

申请日：2004-08-09

申请人： Tetsuya Nitta

发明人： Tetsuya Nitta

IPC分类号： B23Q16/10

CPC分类号： B23Q1/28 ,  B23Q16/102 ,  Y10T74/14 ,  Y10T74/1494

摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.

公开(公告)号：US20080148901A1

公开(公告)日：2008-06-26

申请号：US12068933

申请日：2008-02-13

申请人： Tetsuya Nitta

发明人： Tetsuya Nitta

IPC分类号： B23Q16/10

CPC分类号： B23Q1/28 ,  B23Q16/102 ,  Y10T74/14 ,  Y10T74/1494

摘要： An index table assembly includes a rotary table, a frame separated from the rotary table in the direction of a rotational axis of the rotary table, a clamping device for bringing the rotary table into contact with the frame by moving the rotary table along the rotational axis, a first bearing disposed between the rotary table and the frame, and an urging device disposed between the first bearing and one of the rotary table and the frame and pressing the first bearing against the other one of the rotary table and the frame at least when the rotary table rotates.

摘要翻译： 分度台组件包括旋转台，沿旋转台的旋转轴线的方向与旋转台分离的框架，用于通过沿旋转轴线移动旋转台来使旋转台与框架接触的夹紧装置 设置在所述转台和所述框架之间的第一轴承以及设置在所述第一轴承与所述旋转台和所述框架中的一个之间的推动装置，并且至少在所述旋转台和所述框架中将所述第一轴承压靠在所述旋转台和所述框架中的另一个上时 旋转台旋转。

公开(公告)号：US20090200610A1

公开(公告)日：2009-08-13

申请号：US12401889

申请日：2009-03-11

申请人： Tetsuya Nitta ,  Takayuki Igarashi

发明人： Tetsuya Nitta ,  Takayuki Igarashi

IPC分类号： H01L27/12

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L21/761 ,  H01L21/76281 ,  H01L21/76283 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/0852 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7317 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/7881 ,  H01L29/8611

摘要： An N− layer is formed on a semiconductor substrate, with a BOX layer interposed. In the N− layer, a trench isolation region is formed to surround the N− layer to be an element forming region. The trench isolation region is formed to reach the BOX layer, from the surface of the N− layer. Between trench isolation region and the N− layer, a P type diffusion region 10a is formed. The P type diffusion region is formed continuously without any interruption, to be in contact with the entire surface of an inner sidewall of the trench isolation region surrounding the element forming region. In the element forming region of the N− layer, a prescribed semiconductor element is formed. Thus, a semiconductor device is formed, in which electrical isolation is established reliably, without increasing the area occupied by the element forming region.

摘要翻译： 在半导体衬底上形成有一个BOX层的N层。 在N层中，形成沟槽隔离区域以包围N层以成为元件形成区域。 沟槽隔离区形成为从N层的表面到达BOX层。 在沟槽隔离区域和N层之间形成P型扩散区域10a。 连续形成P型扩散区域而不间断地与围绕元件形成区域的沟槽隔离区域的内侧壁的整个表面接触。 在N层的元件形成区域中，形成规定的半导体元件。 因此，形成了可靠地建立电绝缘的半导体器件，而不增加元件形成区域占据的面积。

公开(公告)号：US20070148874A1

公开(公告)日：2007-06-28

申请号：US11703628

申请日：2007-02-08

申请人： Tetsuya Nitta ,  Tomohide Terashima

发明人： Tetsuya Nitta ,  Tomohide Terashima

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated semiconductor device containing semiconductor elements that have respective desired on-resistances and breakdown voltages achieves appropriate characteristics as a whole of the integrated semiconductor element. The integrated semiconductor device includes a plurality of semiconductor elements formed in a semiconductor layer and each having a source of an n type semiconductor, a drain of the n type semiconductor and a back gate of a p type semiconductor between the source and the drain. At least a predetermined part of the drain of one semiconductor element and a predetermined part of the drain of another semiconductor element have respective impurity concentrations different from each other.

摘要翻译： 包含具有各自期望的导通电阻和击穿电压的半导体元件的集成半导体器件实现了作为整体的集成半导体元件的适当的特性。 集成半导体器件包括形成在半导体层中并且在源极和漏极之间具有n型半导体源，n型半导体的漏极和p型半导体的栅极的多个半导体元件。 至少一个半导体元件的漏极的预定部分和另一个半导体元件的漏极的预定部分具有彼此不同的杂质浓度。