公开(公告)号：US20110309811A1

公开(公告)日：2011-12-22

申请号：US13163908

申请日：2011-06-20

申请人： Katsutoshi KONDO ,  Kazunori Kasuga ,  Hirofumi Shimizu

发明人： Katsutoshi KONDO ,  Kazunori Kasuga ,  Hirofumi Shimizu

IPC分类号： G05F1/00

CPC分类号： H02M3/1584 ,  H02M2001/0032 ,  H02M2001/325 ,  Y02B70/16

摘要： A regulator apparatus having an input terminal and an output terminal, the regulator apparatus includes: a plurality of regulators arranged in parallel between the input terminal and the output terminal; an conversion efficiency characteristic information obtaining unit that obtains conversion efficiency characteristic information representing a characteristic of a conversion efficiency with respect to an output current with regard to each of the plurality of regulators; a memory that stores the conversion efficiency characteristic information of each of the plurality of regulators obtained by the conversion efficiency characteristic information obtaining unit; and a switching control unit that performs a switching control on the plurality of regulators based on a value of the output current output from the output terminal and the conversion efficiency characteristic information stored in the memory.

摘要翻译： 一种具有输入端子和输出端子的调节器装置，所述调节器装置包括：并联设置在所述输入端子和所述输出端子之间的多个调节器; 转换效率特性信息获取单元，获得表示关于多个调节器中的每一个的输出电流的转换效率的特性的转换效率特性信息; 存储器，其存储由所述转换效率特性信息获取单元获得的所述多个调节器中的每一个的转换效率特性信息; 以及开关控制单元，其基于从输出端子输出的输出电流的值和存储在存储器中的转换效率特性信息，对多个调节器进行开关控制。

公开(公告)号：US08680826B2

公开(公告)日：2014-03-25

申请号：US13163908

申请日：2011-06-20

申请人： Katsutoshi Kondo ,  Kazunori Kasuga ,  Hirofumi Shimizu

发明人： Katsutoshi Kondo ,  Kazunori Kasuga ,  Hirofumi Shimizu

IPC分类号： G05F1/59

CPC分类号： H02M3/1584 ,  H02M2001/0032 ,  H02M2001/325 ,  Y02B70/16

摘要： A regulator apparatus having an input terminal and an output terminal, the regulator apparatus includes: a plurality of regulators arranged in parallel between the input terminal and the output terminal; an conversion efficiency characteristic information obtaining unit that obtains conversion efficiency characteristic information representing a characteristic of a conversion efficiency with respect to an output current with regard to each of the plurality of regulators; a memory that stores the conversion efficiency characteristic information of each of the plurality of regulators obtained by the conversion efficiency characteristic information obtaining unit; and a switching control unit that performs a switching control on the plurality of regulators based on a value of the output current output from the output terminal and the conversion efficiency characteristic information stored in the memory.

摘要翻译： 一种具有输入端子和输出端子的调节器装置，所述调节器装置包括：并联设置在所述输入端子和所述输出端子之间的多个调节器; 转换效率特性信息获取单元，获得表示关于多个调节器中的每一个的输出电流的转换效率的特性的转换效率特性信息; 存储器，其存储由所述转换效率特性信息获取单元获得的所述多个调节器中的每一个的转换效率特性信息; 以及开关控制单元，其基于从输出端子输出的输出电流的值和存储在存储器中的转换效率特性信息，对多个调节器进行开关控制。

公开(公告)号：US20100265768A1

公开(公告)日：2010-10-21

申请号：US12815536

申请日：2010-06-15

申请人： Kazunori Kasuga

发明人： Kazunori Kasuga

IPC分类号： G11C16/02 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/10

摘要： A semiconductor storage apparatus comprising: a plurality of cells that store data; a threshold determination section that determines, based on management information that is used to manage data, a binary or multiple-valued form by which values are written to a plurality of the individual cells and determines a threshold based on the determined form of values that are to be written to a plurality of the individual cells; and a write section that writes the data to a plurality of the cells on the basis of the threshold determined by the threshold determination section.

摘要翻译： 一种半导体存储装置，包括：存储数据的多个单元; 阈值确定部分，其基于用于管理数据的管理信息，确定将值写入多个单个小区的二进制或多值形式，并且基于所确定的值形式确定阈值 被写入多个单独的单元; 以及基于由阈值判定部确定的阈值将数据写入多个单元的写入部。

公开(公告)号：US08473674B2

公开(公告)日：2013-06-25

申请号：US12731400

申请日：2010-03-25

申请人： Kazunori Kasuga ,  Osamu Ishibashi

发明人： Kazunori Kasuga ,  Osamu Ishibashi

IPC分类号： G06F12/00

CPC分类号： G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4072 ,  G11C2211/4061 ,  G11C2211/4065

摘要： An information processing device includes a first storage section 2 that includes a plurality of cells to store data; a second storage section 3 that holds refresh intervals and the states of implementation of refresh operations for each of a plurality of the cells; and a control section that controls the refresh operation of each of the cells on the basis of the refresh intervals and the states of implementation of refresh operations held by the second storage section 3. The information processing device controls the refresh operation of each of the cells at refresh intervals set for respective cells.

摘要翻译： 信息处理设备包括：第一存储部分2，其包括用于存储数据的多个单元; 保持刷新间隔的第二存储部3和多个单元中的每一个的刷新动作的执行状态; 以及控制部，其基于所述刷新间隔和由所述第二存储部3保持的刷新动作的执行状态来控制所述单元的刷新动作。所述信息处理装置控制所述单元的刷新动作 在为各个单元设置的刷新间隔。

公开(公告)号：US07978513B2

公开(公告)日：2011-07-12

申请号：US12815536

申请日：2010-06-15

申请人： Kazunori Kasuga

发明人： Kazunori Kasuga

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/10

摘要： A semiconductor storage apparatus comprising: a plurality of cells that store data; a threshold determination section that determines, based on management information that is used to manage data, a binary or multiple-valued form by which values are written to a plurality of the individual cells and determines a threshold based on the determined form of values that are to be written to a plurality of the individual cells; and a write section that writes the data to a plurality of the cells on the basis of the threshold determined by the threshold determination section.

摘要翻译： 一种半导体存储装置，包括：存储数据的多个单元; 阈值确定部分，其基于用于管理数据的管理信息，确定将值写入多个单个小区的二进制或多值形式，并且基于所确定的值形式确定阈值 被写入多个单独的单元; 以及基于由阈值判定部确定的阈值将数据写入多个单元的写入部。

公开(公告)号：US07640425B2

公开(公告)日：2009-12-29

申请号：US11650690

申请日：2007-01-05

申请人： Kazunori Kasuga

发明人： Kazunori Kasuga

IPC分类号： G06F9/24

CPC分类号： G06F9/4406

摘要： A disk apparatus has a memory storing boot-information; and a stop section which reads, upon receipt of a stop event, the boot-information from a disk and checks the read information against the boot-information in the memory. This section updates contents of the memory to store therein the same boot-information as that in the disk and writes flag-information indicating that the same boot-information is stored in the memory when a difference is found by the checking. The apparatus also has a start section which judges, upon receipt of a start event, whether or not the flag-information is stored in the memory, reads the boot-information from the memory and activates a device used with the apparatus while deleting the flag-information when the flag-information is stored. This section reads the boot-information from the disk to activate the device and writes the read boot-information in the memory when the flag-information is not stored.

摘要翻译： 磁盘装置具有存储引导信息的存储器; 以及停止部分，其在接收到停止事件时从盘读取引导信息，并根据存储器中的引导信息检查读取的信息。 该部分更新存储器的内容以存储与盘中的引导信息相同的引导信息，并且当通过检查找到差异时，写入指示将相同引导信息存储在存储器中的标志信息。 该装置还具有起始部，其在接收到开始事件时判断标志信息是否存储在存储器中，从存储器读取引导信息，并在删除标志的同时激活与该装置一起使用的装置 - 存储标志信息时的信息。 本节从磁盘读取引导信息以激活设备，并且在不存储标志信息时将读取的引导信息写入存储器。

公开(公告)号：US08391067B2

公开(公告)日：2013-03-05

申请号：US12623553

申请日：2009-11-23

申请人： Kazunori Kasuga

发明人： Kazunori Kasuga

IPC分类号： G11C11/34

CPC分类号： G11C16/26

摘要： A nonvolatile memory includes a memory cell array including a plurality of memory cells, each of the memory cells capable of storing electric charges nonvolatilly, a first sense amplifier for comparing a voltage produced by one of the selected memory cells to be read out with a first threshold value for distinguishing between a write state and an erase state of the selected memory cell, a second sense amplifier for comparing the voltage produced by one of the selected memory cell with a second threshold value having a greater voltage than the first threshold voltage, and a write unit for rewriting data of the selected memory cell when the first and the second sense amplifiers produce different sense outputs from each other.

摘要翻译： 非易失性存储器包括存储单元阵列，其包括多个存储单元，每个存储单元能够非电容地存储电荷;第一读出放大器，用于将要读出的所选择的存储单元之一产生的电压与第一 用于区分所选存储单元的写入状态和擦除状态的阈值，用于将由所选择的存储单元之一产生的电压与具有比第一阈值电压更大的电压的第二阈值进行比较的第二读出放大器，以及 当第一和第二读出放大器彼此产生不同的感测输出时，用于重写所选存储单元的数据的写入单元。

公开(公告)号：US20070040038A1

公开(公告)日：2007-02-22

申请号：US11287231

申请日：2005-11-28

申请人： Kazunori Kasuga

发明人： Kazunori Kasuga

IPC分类号： G06K19/06

CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/24

摘要： A load detection circuit 40 detects a load value of a load portion 100 via a terminal DQ. A reference load, corresponding to the load of a probe, is output from a reference load output section. A comparison circuit 60 judges whether the detected load value matches the reference load, and outputs a control signal if matched. If this control signal is input, an input and output buffer 30 stops the output of the data from a memory cell 10 to the terminal DQ, or outputs a specific logic.

摘要翻译： 负载检测电路40经由端子DQ检测负载部100的负载值。 从参考负载输出部分输出与探头的负载相对应的参考负载。 比较电路60判断检测到的负载值是否与参考负载相匹配，如果匹配则输出控制信号。 如果输入该控制信号，输入和输出缓冲器30停止将数据从存储器单元10输出到端子DQ，或者输出特定逻辑。

公开(公告)号：US20080040595A1

公开(公告)日：2008-02-14

申请号：US11650690

申请日：2007-01-05

申请人： Kazunori Kasuga

发明人： Kazunori Kasuga

IPC分类号： G06F9/00

CPC分类号： G06F9/4406

摘要： A disk apparatus has a memory storing boot-information; and a stop section which reads, upon receipt of a stop event, the boot-information from a disk and checks the read information against the boot-information in the memory. This section updates contents of the memory to store therein the same boot-information as that in the disk and writes flag-information indicating that the same boot-information is stored in the memory when a difference is found by the checking. The apparatus also has a start section which judges, upon receipt of a start event, whether or not the flag-information is stored in the memory, reads the boot-information from the memory and activates a device used with the apparatus while deleting the flag-information when the flag-information is stored. This section reads the boot-information from the disk to activate the device and writes the read boot-information in the memory when the flag-information is not stored.

摘要翻译： 磁盘装置具有存储引导信息的存储器; 以及停止部分，其在接收到停止事件时从盘读取引导信息，并根据存储器中的引导信息检查读取的信息。 该部分更新存储器的内容以存储与盘中的引导信息相同的引导信息，并且当通过检查找到差异时，写入指示将相同引导信息存储在存储器中的标志信息。 该装置还具有起始部，其在接收到开始事件时判断标志信息是否存储在存储器中，从存储器读取引导信息，并在删除标志的同时激活与该装置一起使用的装置 - 存储标志信息时的信息。 本节从磁盘读取引导信息以激活设备，并且在不存储标志信息时将读取的引导信息写入存储器。

公开(公告)号：US5883839A

公开(公告)日：1999-03-16

申请号：US944552

申请日：1997-10-07

申请人： Masaki Tosaka ,  Yuzo Usui ,  Noriyuki Matsui ,  Masao Matsuda ,  Kazunori Kasuga

发明人： Masaki Tosaka ,  Yuzo Usui ,  Noriyuki Matsui ,  Masao Matsuda ,  Kazunori Kasuga

IPC分类号： G06F13/16 ,  G06F3/00 ,  G06F12/00 ,  G11C5/06 ,  G11C7/00 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401

CPC分类号： G11C5/063 ,  G11C7/00 ,  G11C7/22 ,  G11C8/18

摘要： A memory drive circuit includes at least one memory module constructed of a plurality of memory elements, a memory controller for driving said memory module, and a buffer, disposed between the memory module and the memory controller, for receiving a drive signal from the memory controller and transmitting the received drive signal to the memory module. Signal reflection noises produced in the memory module are absorbed by the buffer.

摘要翻译： 存储器驱动电路包括由多个存储器元件构成的至少一个存储器模块，用于驱动所述存储器模块的存储器控​​制器和设置在存储器模块和存储器控制器之间的缓冲器，用于从存储器控制器接收驱动信号 并将所接收的驱动信号发送到存储器模块。 在存储器模块中产生的信号反射噪声被缓冲器吸收。