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公开(公告)号：US06888488B2
公开(公告)日：2005-05-03
申请号：US10304756
申请日：2002-11-27
摘要： An A/D converter includes a plurality of comparators, each of which samples an analog input potential during a first period, and compares the analog input potential with a reference potential during a second period, an encoder which encodes comparison results obtained by the comparators, and a control signal supply unit which generates one or more control signals that define the first period and the second period such as to make a duration of the first period different from a duration of the send period, and supplies the one or more control signals to the plurality of comparators.
摘要翻译： A / D转换器包括多个比较器，每个比较器在第一周期期间采样模拟输入电位，并且在第二周期期间将模拟输入电位与参考电位进行比较，编码器编码由比较器获得的比较结果， 以及控制信号提供单元，其产生定义第一周期和第二周期的一个或多个控制信号，以使得第一周期的持续时间不同于发送周期的持续时间，并将一个或多个控制信号提供给 多个比较器。
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公开(公告)号：US5495247A
公开(公告)日：1996-02-27
申请号：US109515
申请日：1993-08-20
摘要： There are provided n signal processing units for sampling an analog signal based on n [references] reference voltages, k intermediate signal processing units for comparing two intermediate signals outputted from two adjacent signal processing units in n signal processing units, and an encoder for coding logical output values of the signal processing unit and the intermediate signal processing unit. One signal processing unit includes a differential amplifier, a comparison circuit and logic circuit, and one intermediate signal processing unit includes another comparison circuit and another logic circuit. As a result, when an analog signal is applied to the signal processing unit, a reciprocal of a potential difference between a reference voltage and an analog signal is increased by a gain [times] G, and [the] an intermediate signal is outputted to the comparison circuit of the intermediate signal processing unit. Further, comparison signals of the comparison circuit of the signal processing unit and the comparison circuit of the intermediate signal processing unit are quantized by the logic circuit of the signal processing unit, and comparison signals of the comparison circuit of the intermediate signal processing unit and the comparison circuit of the signal processing unit are quantized by the logic circuit of the intermediate signal processing unit. With this, n+k logical output signals quantized by the logic circuits of n signal processing units and the logic circuits of k intermediate signal processing units are coded by the encoder, thus obtaining a digital output signal in N bits.
摘要翻译： 提供了n个信号处理单元，用于基于n个参考电压对模拟信号进行采样，k个用于比较在n个信号处理单元中从两个相邻信号处理单元输出的两个中间信号的中间信号处理单元和用于编码逻辑的编码器 信号处理单元和中间信号处理单元的输出值。 一个信号处理单元包括差分放大器，比较电路和逻辑电路，一个中间信号处理单元包括另一个比较电路和另一个逻辑电路。 结果，当模拟信号被施加到信号处理单元时，参考电压和模拟信号之间的电位差的倒数增加了增益[times] G，并且将中间信号输出到 中间信号处理单元的比较电路。 此外，信号处理单元的比较电路和中间信号处理单元的比较电路的比较信号由信号处理单元的逻辑电路量化，并且中间信号处理单元的比较电路和 信号处理单元的比较电路由中间信号处理单元的逻辑电路量化。 由此，由n个信号处理单元的逻辑电路和k个中间信号处理单元的逻辑电路量化的n + k逻辑输出信号由编码器编码，从而获得N位的数字输出信号。
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公开(公告)号：US07170556B2
公开(公告)日：2007-01-30
申请号：US10618851
申请日：2003-07-15
申请人： Masatoshi Kokubun , Toshitaka Mizuguchi , Jun Funakoshi , Hiroshi Kobayashi , Katsuyosi Yamamoto
发明人： Masatoshi Kokubun , Toshitaka Mizuguchi , Jun Funakoshi , Hiroshi Kobayashi , Katsuyosi Yamamoto
IPC分类号： H04N5/217
CPC分类号： H04N5/3598
摘要： An image sensor for capturing image, has: a plurality of pixels arranged in a matrix each including a photoelectric conversion element for generating current according to received light intensity and a reset transistor for resetting a node of the photoelectric conversion element to a reset potential; and a sample hold circuit for sample holding a pixel potential according to the potential of the node of the pixel. And the sample hold circuit outputs the differential potential, between a first pixel potential at an end of the integration period after a first reset operation of the pixel and a second pixel potential at an end of a reset noise read period after a second reset operation after the integration period, as a pixel signal. Also in the sample hold circuit, when the second pixel potential during the reset noise read period exceeds a predetermined threshold level, the second pixel potential is set to a predetermined reference potential.
摘要翻译： 一种用于拍摄图像的图像传感器，具有：以矩阵形式排列的多个像素，每个像素包括根据接收光强度产生电流的光电转换元件和用于将光电转换元件的节点复位到复位电位的复位晶体管; 以及用于根据像素的节点的电位保持像素电位的样本的采样保持电路。 并且采样保持电路在第一复位操作之后的积分周期结束时的第一像素电位和第二复位操作之后的复位噪声读取周期结束时的第二像素电位之间输出差分电位 积分期，作为像素信号。 此外，在采样保持电路中，当复位噪声读取周期期间的第二像素电位超过预定阈值电平时，将第二像素电位设置为预定参考电位。
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公开(公告)号：US06914631B2
公开(公告)日：2005-07-05
申请号：US10042240
申请日：2002-01-11
CPC分类号： H04N5/363
摘要： The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device which has a small element size and a wide opening ratio, and can reduce a kTC noise. A photodiode 10, a reset transistor 12, a source follower amplifier 14, and a horizontal selection transistor 16 are formed in each of pixel regions Pmn. A kTC noise reduction circuit 6VR1 for reducing a kTC noise and a CDS circuit 6CL1 are formed outside of the pixel regions Pmn. A differential amplifier is constituted by a first differential transistor 62 of the kTC noise reduction circuit 6VR1 and the source follower amplifier 14 in each of the pixel regions Pmn.
摘要翻译： 本发明涉及一种通过CMOS工艺制造的XY地址型固态摄像装置，其目的是提供一种具有小元件尺寸和宽开口率的XY地址型固态图像拾取装置，并且可以 降低kTC噪声。 在每个像素区域Pmn中形成光电二极管10，复位晶体管12，源极跟随放大器14和水平选择晶体管16。 在像素区域Pmn的外部形成用于降低kTC噪声的kTC噪声降低电路6 VR 1和CDS电路6 CL 1。 差分放大器由每个像素区域Pmn中的kTC降噪电路6 VR 1的第一差分晶体管62和源极跟随放大器14构成。
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5.发明授权X-Y address type solid-state image pickup device with an image averaging circuit disposed in the noise cancel circuit 有权具有设置在噪声消除电路中的图像平均电路的X-Y地址型固态图像拾取装置公开(公告)号：US07242427B2
公开(公告)日：2007-07-10
申请号：US10055901
申请日：2002-01-28
IPC分类号： H04N5/217
摘要： The invention relates to an X-Y address type solid-state image pickup device manufactured by a CMOS process, and has an object to provide an X-Y address type solid-state image pickup device in which a chip area is not increased, manufacturing costs are suppressed, and an image averaging processing can be carried out. Pixel regions Pmn are arranged in a matrix form in regions defined by horizontal selection lines RWm and vertical selection lines CLn. Each of the pixel regions Pmn includes a photodiode 10, a source follower amplifier 14 for converting an electric charge of the photodiode 10 into a voltage and amplifying it to output image data, and a horizontal selection transistor 16 for outputting the image data to a predetermined one of the vertical selection lines CLn. An amplifier/noise cancel circuit 6 has a built-in image averaging circuit for carrying out an averaging processing of the image data outputted from at least two of the plurality of the pixel regions Pmn.
摘要翻译： 本发明涉及一种通过CMOS工艺制造的XY地址型固态摄像装置，其目的是提供一种XY地址型固态摄像装置，其中芯片面积不增加，制造成本被抑制， 并且可以执行图像平均处理。 像素区域Pmn以由水平选择线RWm和垂直选择线CLn限定的区域中的矩阵形式排列。 每个像素区Pmn包括光电二极管10，用于将光电二极管10的电荷转换成电压并放大以输出图像数据的源极跟随器放大器14以及用于将图像数据输出到预定的水平选择晶体管16 垂直选择线CLn之一。 放大器/噪声消除电路6具有内置图像平均电路，用于对从多个像素区域Pmn中的至少两个输出的图像数据进行平均处理。
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6.发明授权CMOS sensor circuit having a voltage control circuit controlling a gate potential of a photodiode reset transistor to a potential other than power source potentials 失效CMOS传感器电路具有将光电二极管复位晶体管的栅极电位控制为电源电位以外的电位的电压控制电路公开(公告)号：US07196726B2
公开(公告)日：2007-03-27
申请号：US10058789
申请日：2002-01-30
CPC分类号： H04N5/3594 , H04N5/374
摘要： The CMOS sensor circuit comprises a photodiode, a reset transistor resetting the photodiode to an initial voltage, and a voltage control circuit controlling a gate potential of the reset transistor to a potential other than power source potentials. The voltage control circuit consists of an inverter circuit driving a gate of the reset transistor. The inverter circuit includes a P-channel MOS transistor, an N-channel MOS transistor, and a transistor inserted between a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor so as to control a blooming.
摘要翻译： CMOS传感器电路包括光电二极管，将光电二极管复位为初始电压的复位晶体管，以及将复位晶体管的栅极电位控制为电源电位以外的电位的电压控制电路。 电压控制电路由驱动复位晶体管的栅极的逆变器电路构成。 逆变器电路包括P沟道MOS晶体管，N沟道MOS晶体管和插入在P沟道MOS晶体管的漏极和N沟道MOS晶体管的漏极之间的晶体管，以便控制着色。
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公开(公告)号：US20060250513A1
公开(公告)日：2006-11-09
申请号：US11484741
申请日：2006-07-12
申请人： Katsuyosi Yamamoto , Jun Funakoshi
发明人： Katsuyosi Yamamoto , Jun Funakoshi
IPC分类号： H04N5/335
CPC分类号： H04N5/361 , H04N5/23241 , H04N5/3745
摘要： The control inputs of reset switch elements 41 to 45 are commonly connected to a row reset line 51. In a line black clamp type, cathodes as reset ends of photodiodes (31) of optical black pixels 21 to 23 are commonly connected to a potential averaging line 30. In a frame black clamp type, potential averaging lines are connected similarly to respective pixel rows on the vertical scanning start side of an optical black pixel region, and the potential averaging lines may be commonly connected to each other to operate just like one pixel row. A first block includes a pixel array and a vertical scanning circuit, while a second block includes sample and hold circuits, a horizontal scanning circuit, an amplifier and an A/D converter 19. In a low power consumption mode, power supply to the second block is ceased in a light integration period of one frame with performing light integration in the pixel array, power supply to the first and second blocks is performed in a read-out period of one frame to read out integrated signals, and power supply to the first and second blocks is ceased in a power-off period of one frame.
摘要翻译： 复位开关元件41至45的控制输入通常连接到行复位线51。 在黑色夹线型中，作为光学黑色像素21至23的光电二极管（31）的复位端的阴极通常连接到电位平均线30。 在帧黑钳型中，电位平均线与光学黑色像素区域的垂直扫描开始侧的各个像素行类似地连接，并且电位平均线可以相互共同连接以像一个像素行那样操作。 第一块包括像素阵列和垂直扫描电路，而第二块包括采样和保持电路，水平扫描电路，放大器和A / D转换器19。 在低功耗模式中，通过在像素阵列中执行光积分，在一帧的光积分周期内停止对第二块的电源，在第一和第二块的读出周期中执行向第一和第二块的电力供应 帧读出集成信号，并且在一帧的断电期间停止对第一和第二块的电力供应。
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公开(公告)号：US07098950B2
公开(公告)日：2006-08-29
申请号：US09785330
申请日：2001-02-20
申请人： Katsuyosi Yamamoto , Jun Funakoshi
发明人： Katsuyosi Yamamoto , Jun Funakoshi
IPC分类号： H04N9/64
CPC分类号： H04N5/361 , H04N5/23241 , H04N5/3745
摘要： The control inputs of reset switch elements 41 to 45 are commonly connected to a row reset line 51. In a line black clamp type, cathodes as reset ends of photodiodes (31) of optical black pixels 21 to 23 are commonly connected to a potential averaging line 30. In a frame black clamp type, potential averaging lines are connected similarly to respective pixel rows on the vertical scanning start side of an optical black pixel region, and the potential averaging lines may be commonly connected to each other to operate just like one pixel row. A first block includes a pixel array and a vertical scanning circuit, while a second block includes sample and hold circuits, a horizontal scanning circuit, an amplifier and an A/D converter 19. In a low power consumption mode, power supply to the second block is ceased in a light integration period of one frame with performing light integration in the pixel array, power supply to the first and second blocks is performed in a read-out period of one frame to read out integrated signals, and power supply to the first and second blocks is ceased in a power-off period of one frame.
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