公开(公告)号：US07125792B2

公开(公告)日：2006-10-24

申请号：US10685055

申请日：2003-10-14

申请人： Kaushik Kumar ,  Douglas C. La Tulipe ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht

发明人： Kaushik Kumar ,  Douglas C. La Tulipe ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  H01J37/32862 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76811

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

摘要翻译： 一种双镶嵌结构及其制造方法。 绝缘层包括第一介电材料和第二电介质材料，第二电介质材料不同于第一电介质材料。 具有第一图案的第一导电区域形成在第一电介质材料中，并且具有第二图案的第二导电区域形成在第二电介质材料中，第二图案不同于第一图案。 第一电介质材料和第二电介质材料之一包括有机材料，而另一介电材料包括无机材料。 第一和第二介电材料之一是可蚀刻的对另一种介电材料的选择性。 还公开了当晶片保持在室内时清洁半导体晶片处理室的方法。

公开(公告)号：US07091612B2

公开(公告)日：2006-08-15

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US07241681B2

公开(公告)日：2007-07-10

申请号：US11330834

申请日：2006-01-12

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US07052621B2

公开(公告)日：2006-05-30

申请号：US10461090

申请日：2003-06-13

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： C23F1/00

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US20050077628A1

公开(公告)日：2005-04-14

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US20050079706A1

公开(公告)日：2005-04-14

申请号：US10685055

申请日：2003-10-14

申请人： Kaushik Kumar ,  Douglas La Tulipe ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht

发明人： Kaushik Kumar ,  Douglas La Tulipe ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76835 ,  H01J37/32862 ,  H01L21/02046 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76811

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

摘要翻译： 一种双镶嵌结构及其制造方法。 绝缘层包括第一介电材料和第二电介质材料，第二电介质材料不同于第一电介质材料。 具有第一图案的第一导电区域形成在第一电介质材料中，并且具有第二图案的第二导电区域形成在第二电介质材料中，第二图案与第一图案不同。 第一电介质材料和第二电介质材料之一包括有机材料，而另一介电材料包括无机材料。 第一和第二介电材料之一是可蚀刻的对另一种介电材料的选择性。 还公开了当晶片保持在室内时清洁半导体晶片处理室的方法。

公开(公告)号：US20060113278A1

公开(公告)日：2006-06-01

申请号：US11330834

申请日：2006-01-12

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew Simon ,  Mark Hoinkis ,  Steffen Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew Simon ,  Mark Hoinkis ,  Steffen Kaldor ,  Chih-Chao Yang

IPC分类号： B44C1/22 ,  H01B13/00

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US20050112864A1

公开(公告)日：2005-05-26

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US20060292852A1

公开(公告)日：2006-12-28

申请号：US11463447

申请日：2006-08-09

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US20050208742A1

公开(公告)日：2005-09-22

申请号：US10708648

申请日：2004-03-17

申请人： William America ,  Larry Clevenger ,  Andy Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Kaushik Kumar ,  Douglas La Tulipe

发明人： William America ,  Larry Clevenger ,  Andy Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Kaushik Kumar ,  Douglas La Tulipe

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76811 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76834

摘要： A method of producing an oxidized tantalum nitride (TaOxNx) hardmask layer for use in dual-damascene processing is described. Fine-line dual-damascene processing places competing, conflicting demands on the hardmask. Whereas critical dimension control needs a thicker hardmask, optical lithographic alignment is frustrated by the opacity of thick tantalum nitride (TaN). The technique solves the problem of TaN hardmask opacity with increasing thickness by oxidizing the TaN layer. Oxidation of the TaN hardmask increases the thickness of the hardmask to two to four times its original thickness and simultaneously increases its transparency by greater than ten times. This permits better CD control associated with a thicker hardmask while facilitating optical lithographic alignment.

摘要翻译： 描述了用于双镶嵌加工的氧化氮化钽（TaO x N N N x S）硬掩模层的制造方法。 精细的双镶嵌加工对硬掩模产生了竞争，冲突的要求。 尽管临界尺寸控制需要较厚的硬掩模，但由于厚氮化钽（TaN）的不透明度，光学平版印刷对挫败感到沮丧。 该技术通过氧化TaN层来解决厚度增加的TaN硬掩模不透明度问题。 TaN硬掩模的氧化将硬掩模的厚度增加到其原始厚度的两到四倍，同时将其透明度提高了十倍以上。 这允许与更厚的硬掩模相关联的更好的CD控制，同时促进光学光刻对准。