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公开(公告)号：US20090065929A1
公开(公告)日：2009-03-12
申请号：US12264970
申请日：2008-11-05
申请人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
发明人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
IPC分类号： H01L23/34
CPC分类号： H01L27/14618 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/14634 , H01L2224/05553 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48644 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/85444 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes semiconductor chips differing in withstand voltage or in noise immunity, such as a multi-chip module. The semiconductor device includes first and second semiconductor chips mounted over a package substrate which has bonding pads arranged along the edges. The first semiconductor chip includes bonding pads for analog signals, and the second semiconductor chip includes bonding pads for high-voltage signals. The edges along which the bonding pads for analog signals are arranged and the edges along which the bonding pads for high-voltage signals are arranged are disposed along mutually different edges of the package substrate. Adjoining of electrodes or wirings for high voltage signals and those for analog signals over the package substrate can be easily avoided, and SI deterioration can be thereby restrained.
摘要翻译： 半导体器件包括不同于耐电压或抗噪声的诸如多芯片模块的半导体芯片。 半导体器件包括安装在封装衬底上的第一和第二半导体芯片，该封装衬底具有沿边缘布置的焊盘。 第一半导体芯片包括用于模拟信号的接合焊盘，第二半导体芯片包括用于高电压信号的焊盘。 布置用于模拟信号的接合焊盘的边缘以及布置有用于高电压信号的接合焊盘的边缘沿着封装衬底的相互不同的边缘设置。 可以容易地避免用于高电压信号的电极或布线与封装基板上的模拟信号的连接，从而可以抑制SI劣化。
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公开(公告)号：US07462929B2
公开(公告)日：2008-12-09
申请号：US11392730
申请日：2006-03-30
申请人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
发明人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
CPC分类号： H01L27/14618 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/14634 , H01L2224/05553 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48644 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/85444 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： SI in a semiconductor device in which a plurality of semiconductor chips differing in withstand voltage or in noise immunity, such as a multi-chip module, is to be improved. The semiconductor device comprises a first semiconductor chip and a second semiconductor chip mounted over a package substrate which has a plurality of bonding pads arranged along the edges. The first semiconductor chip has a plurality of bonding pads for analog signals, and the second semiconductor chip has a plurality of bonding pads for high-voltage signals. The edges along which the bonding pads for analog signals are arranged and the edges along which the bonding pads for high-voltage signals are arranged are disposed along mutually different edges of the package substrate. Adjoining of electrodes or wirings for high voltage signals and those for analog signals over the package substrate can be easily avoided, and SI deterioration can be thereby restrained.
摘要翻译： 要提高其中诸如多芯片模块之类的耐电压或抗噪声能力不同的多个半导体芯片的半导体器件中的SI。 半导体器件包括安装在封装衬底上的第一半导体芯片和第二半导体芯片，该封装衬底具有沿着边缘布置的多个焊盘。 第一半导体芯片具有用于模拟信号的多个接合焊盘，第二半导体芯片具有用于高电压信号的多个焊盘。 布置用于模拟信号的接合焊盘的边缘以及布置有用于高电压信号的接合焊盘的边缘沿着封装衬底的相互不同的边缘设置。 可以容易地避免用于高电压信号的电极或布线与封装基板上的模拟信号的连接，从而可以抑制SI劣化。
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公开(公告)号：US07745921B2
公开(公告)日：2010-06-29
申请号：US12264970
申请日：2008-11-05
申请人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
发明人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
IPC分类号： H01L23/02
CPC分类号： H01L27/14618 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/14634 , H01L2224/05553 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48644 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/85444 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes semiconductor chips differing in withstand voltage or in noise immunity, such as a multi-chip module. The semiconductor device includes first and second semiconductor chips mounted over a package substrate which has bonding pads arranged along the edges. The first semiconductor chip includes bonding pads for analog signals, and the second semiconductor chip includes bonding pads for high-voltage signals. The edges along which the bonding pads for analog signals are arranged and the edges along which the bonding pads for high-voltage signals are arranged are disposed along mutually different edges of the package substrate. Adjoining of electrodes or wirings for high voltage signals and those for analog signals over the package substrate can be easily avoided, and SI deterioration can be thereby restrained.
摘要翻译： 半导体器件包括不同于耐电压或抗噪声的诸如多芯片模块的半导体芯片。 半导体器件包括安装在封装衬底上的第一和第二半导体芯片，该封装衬底具有沿边缘布置的焊盘。 第一半导体芯片包括用于模拟信号的接合焊盘，第二半导体芯片包括用于高电压信号的焊盘。 布置用于模拟信号的接合焊盘的边缘以及布置有用于高电压信号的接合焊盘的边缘沿着封装衬底的相互不同的边缘设置。 可以容易地避免用于高电压信号的电极或布线与封装基板上的模拟信号的连接，从而可以抑制SI劣化。
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公开(公告)号：US20060220673A1
公开(公告)日：2006-10-05
申请号：US11392730
申请日：2006-03-30
申请人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
发明人： Kazuhiko Hiranuma , Hiroshi Kuroda , Yoshiyuki Abe
IPC分类号： H03K17/16
CPC分类号： H01L27/14618 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/14634 , H01L2224/05553 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48644 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2224/85444 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2225/06586 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： SI in a semiconductor device in which a plurality of semiconductor chips differing in withstand voltage or in noise immunity, such as a multi-chip module, is to be improved. The semiconductor device comprises a first semiconductor chip and a second semiconductor chip mounted over a package substrate which has a plurality of bonding pads arranged along the edges. The first semiconductor chip has a plurality of bonding pads for analog signals, and the second semiconductor chip has a plurality of bonding pads for high-voltage signals. The edges along which the bonding pads for analog signals are arranged and the edges along which the bonding pads for high-voltage signals are arranged are disposed along mutually different edges of the package substrate. Adjoining of electrodes or wirings for high voltage signals and those for analog signals over the package substrate can be easily avoided, and SI deterioration can be thereby restrained.
摘要翻译： 要提高其中诸如多芯片模块之类的耐电压或抗噪声能力不同的多个半导体芯片的半导体器件中的SI。 半导体器件包括安装在封装衬底上的第一半导体芯片和第二半导体芯片，该封装衬底具有沿着边缘布置的多个焊盘。 第一半导体芯片具有用于模拟信号的多个接合焊盘，第二半导体芯片具有用于高电压信号的多个焊盘。 布置用于模拟信号的接合焊盘的边缘以及布置有用于高电压信号的接合焊盘的边缘沿着封装衬底的相互不同的边缘设置。 可以容易地避免用于高电压信号的电极或布线与封装基板上的模拟信号的连接，从而可以抑制SI劣化。
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公开(公告)号：US07656039B2
公开(公告)日：2010-02-02
申请号：US11563416
申请日：2006-11-27
申请人： Hiroshi Kuroda , Kazuhiko Hiranuma
发明人： Hiroshi Kuroda , Kazuhiko Hiranuma
CPC分类号： H01L25/0657 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06555 , H01L2225/06575 , H01L2225/06586 , H01L2225/06596 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： The present invention provides a multi chip module which realizes high functions or high performances thereof. A multi chip module is constituted by stacking a first semiconductor chip on which a digital signal processing circuit is mounted, a second semiconductor chip which constitutes a dynamic random access memory, a third semiconductor chip which constitutes a non-volatile memory, and a mounting substrate thus forming the stacked structure. The first semiconductor chip is arranged on an uppermost layer with a spacer interposed on a back surface side thereof. The second semiconductor chip is arranged on the mounting substrate.
摘要翻译： 本发明提供实现高功能或高性能的多芯片模块。 多芯片模块通过堆叠安装有数字信号处理电路的第一半导体芯片，构成动态随机存取存储器的第二半导体芯片，构成非易失性存储器的第三半导体芯片和安装基板 从而形成堆叠结构。 第一半导体芯片布置在最上层，隔离件插入其背面侧。 第二半导体芯片布置在安装基板上。
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公开(公告)号：US20070120267A1
公开(公告)日：2007-05-31
申请号：US11563416
申请日：2006-11-27
申请人： Hiroshi KURODA , Kazuhiko Hiranuma
发明人： Hiroshi KURODA , Kazuhiko Hiranuma
CPC分类号： H01L25/0657 , H01L2224/48227 , H01L2224/49171 , H01L2225/0651 , H01L2225/06555 , H01L2225/06575 , H01L2225/06586 , H01L2225/06596 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： The present invention provides a multi chip module which realizes high functions or high performances thereof. A multi chip module is constituted by stacking a first semiconductor chip on which a digital signal processing circuit is mounted, a second semiconductor chip which constitutes a dynamic random access memory, a third semiconductor chip which constitutes a non-volatile memory, and a mounting substrate thus forming the stacked structure. The first semiconductor chip is arranged on an uppermost layer with a spacer interposed on a back surface side thereof. The second semiconductor chip is arranged on the mounting substrate.
摘要翻译： 本发明提供实现高功能或高性能的多芯片模块。 多芯片模块通过堆叠安装有数字信号处理电路的第一半导体芯片，构成动态随机存取存储器的第二半导体芯片，构成非易失性存储器的第三半导体芯片和安装基板 从而形成堆叠结构。 第一半导体芯片布置在最上层，隔离件插入其背面侧。 第二半导体芯片布置在安装基板上。
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公开(公告)号：US09390766B2
公开(公告)日：2016-07-12
申请号：US13372425
申请日：2012-02-13
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H01L2224/32225 , H01L2224/48465 , H01L2224/73265
摘要： There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path.
摘要翻译： 需要提供能够容易地允许旁路电容器总是改善信号路径上的噪声抑制的半导体器件和电子器件，以便以不同的电源噪声状态在芯片之间传输参考电位。 提供了连接控制芯片和安装在安装基板上的存储芯片的指定信号路径，并传输从控制芯片产生的参考电位。 旁路电容器仅在连接部分处连接到指定的信号路径，在连接部分处，沿着指定信号路径的存储芯片的参考电位焊盘到连接部分的距离短于距控制芯片的参考电位焊盘的距离 沿着指定的信号路径连接到连接部分。
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公开(公告)号：US20120206954A1
公开(公告)日：2012-08-16
申请号：US13372425
申请日：2012-02-13
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H01L2224/32225 , H01L2224/48465 , H01L2224/73265
摘要： There is a need to provide a semiconductor device and an electronic device capable of easily allowing a bypass capacitor to always improve noise suppression on a signal path in order to transmit a reference potential between chips in different power supply noise states. There is provided a specified signal path that connects a control chip and a memory chip mounted on a mounting substrate and transmits a reference potential generated from the control chip. A bypass capacitor is connected to the specified signal path only at a connecting part where a distance from a reference potential pad of the memory chip to the connecting part along the specified signal path is shorter than a distance from a reference potential pad of the control chip to the connecting part along the specified signal path.
摘要翻译： 需要提供能够容易地允许旁路电容器总是改善信号路径上的噪声抑制的半导体器件和电子器件，以便以不同的电源噪声状态在芯片之间传输参考电位。 提供了连接控制芯片和安装在安装基板上的存储芯片的指定信号路径，并传输从控制芯片产生的参考电位。 旁路电容器仅在连接部分处连接到指定的信号路径，在连接部分处，沿着指定信号路径的存储芯片的参考电位焊盘到连接部分的距离短于距控制芯片的参考电位焊盘的距离 沿着指定的信号路径连接到连接部分。
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