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    Semiconductor Integrated Circuit Device Operating in Synchronism with Clock and Method for Controlling Duty of Clock
    1.
    发明申请
    Semiconductor Integrated Circuit Device Operating in Synchronism with Clock and Method for Controlling Duty of Clock 失效
    与时钟同步工作的半导体集成电路器件和用于控制时钟占空比的方法

    公开(公告)号：US20080191768A1

    公开(公告)日：2008-08-14

    申请号：US12027101

    申请日：2008-02-06

    申请人： Kazuhiko Miki ,  Yutaka Nakamura

    发明人： Kazuhiko Miki ,  Yutaka Nakamura

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  G06F1/12

    摘要： A semiconductor integrated circuit device includes a processor, a first clock generating section and a control section. The processor core operates in synchronism with a first clock and includes first and second critical paths. The first clock generating section controls a duty of an externally input second clock to generate the first clock. a control section detects a first phase difference between the first clock and a third clock obtained by delaying the first clock by a delay time in the first critical path and a second phase difference between the first clock and a fourth clock obtained by delaying the first clock by a delay time in the second critical path. The control section instructs the first clock generating section to control the duty so as to minimize a difference between the first and second phase differences.

    摘要翻译： 半导体集成电路器件包括处理器，第一时钟产生部分和控制部分。 处理器核与第一时钟同步操作，并且包括第一和第二关键路径。 第一时钟产生部分控制外部输入的第二时钟的占空比以产生第一时钟。 控制部分检测第一时钟与通过将第一时钟延迟第一关键路径中的延迟时间而获得的第三时钟之间的第一相位差，以及通过延迟第一时钟而获得的第一时钟与第四时钟之间的第二相位差 在第二个关键路径中延迟时间。 控制部分指示第一时钟产生部分控制占空比，以使第一和第二相位差之间的差最小化。

    Semiconductor integrated circuit device operating in synchronism with clock and method for controlling duty of clock
    2.
    发明授权
    Semiconductor integrated circuit device operating in synchronism with clock and method for controlling duty of clock 失效
    半导体集成电路器件与时钟同步工作，控制时钟的占空比

    公开(公告)号：US07724056B2

    公开(公告)日：2010-05-25

    申请号：US12027101

    申请日：2008-02-06

    申请人： Kazuhiko Miki ,  Yutaka Nakamura

    发明人： Kazuhiko Miki ,  Yutaka Nakamura

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565 ,  G06F1/12

    摘要： A semiconductor integrated circuit device includes a processor, a first clock generating section and a control section. The processor core operates in synchronism with a first clock and includes first and second critical paths. The first clock generating section controls a duty of an externally input second clock to generate the first clock. a control section detects a first phase difference between the first clock and a third clock obtained by delaying the first clock by a delay time in the first critical path and a second phase difference between the first clock and a fourth clock obtained by delaying the first clock by a delay time in the second critical path. The control section instructs the first clock generating section to control the duty so as to minimize a difference between the first and second phase differences.

    摘要翻译： 半导体集成电路器件包括处理器，第一时钟产生部分和控制部分。 处理器核与第一时钟同步操作，并且包括第一和第二关键路径。 第一时钟产生部分控制外部输入的第二时钟的占空比以产生第一时钟。 控制部分检测第一时钟与通过将第一时钟延迟第一关键路径中的延迟时间而获得的第三时钟之间的第一相位差，以及通过延迟第一时钟而获得的第一时钟与第四时钟之间的第二相位差 在第二个关键路径中延迟时间。 控制部分指示第一时钟产生部分控制占空比，以使第一和第二相位差之间的差最小化。

    Manual surveying instrument having collimation assisting device
    5.
    发明授权
    Manual surveying instrument having collimation assisting device 有权
    具有准直辅助装置的手动测量仪器

    公开(公告)号：US08225518B2

    公开(公告)日：2012-07-24

    申请号：US13057785

    申请日：2009-05-29

    申请人： Satoshi Yanobe ,  Yutaka Nakamura

    发明人： Satoshi Yanobe ,  Yutaka Nakamura

    IPC分类号： G01C5/00

    CPC分类号： G01C15/00

    摘要： [Problem] To provide a manual surveying instrument that allows easily performing a collimating operation and allows performing a high precision measurement in a short time.[Solution Means] The manual surveying instrument includes a collimation assist device (70) having a collimation light transmitting system that emits a collimation light (R) along a collimation axis (O) toward a target installed at a measurement point, an area sensor (80) that obtains an image of a scene captured within a field of view of a collimating telescope (3), a display unit (48) that displays the image, a collimation light detecting unit (82) that detects the target as a result of receiving the collimation light reflected on the target by the area sensor, and an arithmetic control unit (46) that displays an area (94) being within a predetermined deviation from the collimation axis and where distance measurement is possible and a symbol indicating the target on the display unit as an animation image, judges that collimation has been completed when the target has been captured, by a manual operation of the collimating telescope, within the area where distance measurement is possible to perform a distance and angle measurement, and corrects an angle measurement value according to a deviation from the collimation axis of the target.

    摘要翻译： [问题]提供一种能够容易地进行准直操作并允许在短时间内执行高精度测量的手动测量仪器。 [解决方案]手动测量仪器包括准直辅助装置（70），准直辅助装置（70）具有准直光传输系统，其沿着准直轴（O）向安装在测量点处的目标发射准直光（R），区域传感器 80），其获得在准直望远镜（3）的视野内拍摄的场景的图像，显​​示图像的显示单元（48）;作为结果的结果检测目标的准直光检测单元（82） 接收由所述区域传感器反射在所述目标上的准直光;以及运算控制单元，其显示与所述准直轴在预定偏差内的区域（94），并且能够进行距离测量，以及指示所述目标的符号 显示单元作为动画图像，通过准直望远镜的手动操作，在可能进行距离测量的区域内，判断已经捕获目标时的准直已经完成 执行距离和角度测量，并根据与目标的准直轴的偏差来校正角度测量值。

    Order supporting system, order supporting method, and recording medium
    6.
    发明授权
    Order supporting system, order supporting method, and recording medium 有权
    订单支持系统，订单支持方式和记录介质

    公开(公告)号：US08005725B2

    公开(公告)日：2011-08-23

    申请号：US11798756

    申请日：2007-05-16

    申请人： Masato Takahashi ,  Keiji Nagai ,  Koji Dan ,  Yutaka Nakamura ,  Yuuki Inoue ,  Fujio Takahashi ,  Shogo Hyakutake ,  Yoshiaki Murata ,  Kenichi Takeda

    发明人： Masato Takahashi ,  Keiji Nagai ,  Koji Dan ,  Yutaka Nakamura ,  Yuuki Inoue ,  Fujio Takahashi ,  Shogo Hyakutake ,  Yoshiaki Murata ,  Kenichi Takeda

    IPC分类号： G06Q30/00 ,  G06Q10/00

    CPC分类号： G03G15/55 ,  G03G15/5079 ,  G03G15/553 ,  G06Q10/087 ,  G06Q30/0601 ,  G06Q30/0633

    摘要： An order supporting system includes a machine monitoring apparatus including an obtaining part for repetitively obtaining status data of plural supplies of plural machines connected to a network, a storing part for storing the status data obtained by the obtaining part, a detecting part for detecting change in the status of the supply by comparing the status data stored in the storing part and new status data that is newly obtained by the obtaining part, and a transmitting part for transmitting status data corresponding to the supply of the machine from which status change is detected by the detecting part, and an order supporting apparatus for receiving the status data transmitted from the transmitting part via the network and transmitting an electronic mail to a mail address associated to the machine corresponding to the transmitted status data in accordance with the received status data.

    摘要翻译： 订单支持系统包括：机器监视装置，包括：重复获取连接到网络的多个机器的多个供应的状态数据的获取部，用于存储由获取部获得的状态数据的存储部;检测部， 通过比较存储在存储部分中的状态数据和由获取部分新获得的新状态数据来提供供应的状态，以及发送部分，用于发送对应于通过以下步骤检测到状态改变的机器供应的状态数据： 检测部分和用于经由网络接收从发送部分发送的状态数据的订单支持装置，并且根据接收到的状态数据将电子邮件发送到与发送的状态数据相对应的与机器相关联的邮件地址。

    Dynamic semiconductor storage device and method for operating same
    8.
    发明授权
    Dynamic semiconductor storage device and method for operating same 失效
    动态半导体存储装置及其操作方法

    公开(公告)号：US07616510B2

    公开(公告)日：2009-11-10

    申请号：US11848401

    申请日：2007-08-31

    申请人： Yutaka Nakamura

    发明人： Yutaka Nakamura

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4094 ,  G11C11/4099

    摘要： The object of the present invention is to provide a DRAM, in which the operation speed for a sense amplifier can be increased. Bit line precharging circuits PCt and PCb are arranged to precharge bit lines BLt and /BLt to a ground voltage GND, and reference word lines RWLo and RWLe and reference memory cells RMC are arranged, so that when a word line WL is activated, a potential difference is always generated between the bit lines BLt and /BLt. The sources of transistors N10 and N11 of an N-type sense amplifier NSAt are connected directly to a ground terminal GND, and the sources of transistors P2 and P3 of a P-type sense amplifier PSA are connected directly to a power source VDD. The gates of the transistors N10 and N11 are connected to the bit lines /BLt and BLt, and the drains are connected to the bit lines BLt and /BLt, respectively. Shift word lines SWL and shift memory cells SMC are arranged, so that the N sense amplifier NSAt can amplify the potential difference between the bit lines BLt and /BLt.

    摘要翻译： 本发明的目的是提供一种DRAM，其中可以增加读出放大器的操作速度。 位线预充电电路PCt和PCb布置成将位线BLt和/ BLt预充电到地电压GND，并且布置参考字线RWLo和RWLe以及参考存储单元RMC，使得当字线WL被激活时， 总是在位线BLt和/ BLt之间产生差异。 N型读出放大器NSAt的晶体管N10和N11的源极直接连接到接地端子GND，P型读出放大器PSA的晶体管P2和P3的源极直接连接到电源VDD。 晶体管N10和N11的栅极连接到位线BLt和BLt，漏极分别连接到位线BLt和/ BLt。 移位字线SWL和移位存储器单元SMC被布置，使得N个读出放大器NSAt可以放大位线BLt和/ BLt之间的电位差。

    IC card
    9.
    发明授权
    IC card 失效
    IC卡

    公开(公告)号：US07616447B2

    公开(公告)日：2009-11-10

    申请号：US11629789

    申请日：2005-06-17

    申请人： Hiroyuki Yamada ,  Yoshiteru Mori ,  Kenji Nishimura ,  Yutaka Nakamura

    发明人： Hiroyuki Yamada ,  Yoshiteru Mori ,  Kenji Nishimura ,  Yutaka Nakamura

    IPC分类号： H05K1/14

    CPC分类号： G06K19/07345 ,  G06K19/07732

    摘要： An IC memory card (11) has a mode change switch (18) for switching operation modes of a semiconductor component in the vicinity of an end side opposite the external connection terminals (17a to 17i). A controller LSI (24) detects the status of the mode change switch (18) and switches operation modes according to the detected status.

    摘要翻译： IC存储卡（11）具有用于切换与外部连接端子（17a至17i）相对的端侧附近的半导体部件的操作模式的模式切换开关（18）。 控制器LSI（24）根据检测到的状态检测模式切换开关（18）的状态并切换动作模式。