公开(公告)号：US20060097356A1

公开(公告)日：2006-05-11

申请号：US11062488

申请日：2005-02-23

申请人： Shigeru Fujii ,  Yoshikazu Arisaka ,  Hitoshi Izuru ,  Kazuhiro Tashiro ,  Shigeyuki Maruyama

发明人： Shigeru Fujii ,  Yoshikazu Arisaka ,  Hitoshi Izuru ,  Kazuhiro Tashiro ,  Shigeyuki Maruyama

IPC分类号： H01L23/544

CPC分类号： H01L21/78 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.

摘要翻译： 半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。 多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。 第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。 第二划线在单元曝光和打印区域之间延伸。 第一划线的宽度与第二划线的宽度不同。

公开(公告)号：US20070170425A1

公开(公告)日：2007-07-26

申请号：US11411877

申请日：2006-04-27

申请人： Kazuhiro Tashiro ,  Hitoshi Izuru

发明人： Kazuhiro Tashiro ,  Hitoshi Izuru

IPC分类号： H01L23/58

CPC分类号： H01L22/32 ,  G01R31/2863 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3512 ,  H01L2924/00

摘要： The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g. test pads 13, can be electrically connected to an external test apparatus when the semiconductor integrated circuit devices 14 and 16 are electrically connected to the circuit board 12.

摘要翻译： 本发明提供了一种高质量的半导体集成电路器件，其中半导体集成电路器件，SiP或特别是PoP半导体集成电路器件能够同时测试多个上下半导体集成电路元件的可靠性; 它还能够在另一个被确定有缺陷的情况下仅测试无缺陷元件; 此外，只有有缺陷的单元可与无缺陷单元交换。 本发明的半导体集成电路器件包含多个半导体集成电路元件，例如 半导体集成电路器件14和16以及中继各个半导体集成电路元件14和16以及电路板12的至少一部分的电路板12，例如， 当半导体集成电路器件14和16电连接到电路板12时，测试焊盘13可以电连接到外部测试装置。

公开(公告)号：US07915720B2

公开(公告)日：2011-03-29

申请号：US11411877

申请日：2006-04-27

申请人： Kazuhiro Tashiro ,  Hitoshi Izuru

发明人： Kazuhiro Tashiro ,  Hitoshi Izuru

IPC分类号： H01L23/02

CPC分类号： H01L22/32 ,  G01R31/2863 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3512 ,  H01L2924/00

摘要： The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g. test pads 13, can be electrically connected to an external test apparatus when the semiconductor integrated circuit devices 14 and 16 are electrically connected to the circuit board 12.

摘要翻译： 本发明提供了一种高质量的半导体集成电路器件，其中半导体集成电路器件，SiP或特别是PoP半导体集成电路器件能够同时测试多个上下半导体集成电路元件的可靠性; 它还使得仅在确定有缺陷的情况下仅测试无缺陷元件; 此外，只有有缺陷的单元可与无缺陷单元交换。 本发明的半导体集成电路器件包含多个半导体集成电路元件，例如 半导体集成电路器件14和16以及中继各个半导体集成电路元件14和16以及电路板12的至少一部分的电路板12，例如， 当半导体集成电路器件14和16电连接到电路板12时，测试焊盘13可以电连接到外部测试装置。

公开(公告)号：US20080227226A1

公开(公告)日：2008-09-18

申请号：US12153481

申请日：2008-05-20

申请人： Shigeru Fujii ,  Yoshikazu Arisaka ,  Hitoshi Izuru ,  Kazuhiro Tashiro ,  Shigeyuki Maruyama

发明人： Shigeru Fujii ,  Yoshikazu Arisaka ,  Hitoshi Izuru ,  Kazuhiro Tashiro ,  Shigeyuki Maruyama

IPC分类号： H01L21/66 ,  H01L21/304

CPC分类号： H01L21/78 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.

摘要翻译： 半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。 多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。 第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。 第二划线在单元曝光和打印区域之间延伸。 第一划线的宽度与第二划线的宽度不同。

公开(公告)号：US07199600B2

公开(公告)日：2007-04-03

申请号：US11078352

申请日：2005-03-14

申请人： Hitoshi Izuru ,  Kazuhiro Tashiro

发明人： Hitoshi Izuru ,  Kazuhiro Tashiro

IPC分类号： G01R31/26

CPC分类号： G01R31/2849

摘要： A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.

摘要翻译： 一种老化测试方法，用于在规定温度的大气中操作的半导体器件进行测试，其特征在于，在向半导体器件供电的同时，重复地提供指示半导体器件的操作的操作指令信号，并且增加和减少 对与操作指示信号相对应的电源电流进行计数。

公开(公告)号：US20060061379A1

公开(公告)日：2006-03-23

申请号：US11078352

申请日：2005-03-14

申请人： Hitoshi Izuru ,  Kazuhiro Tashiro

发明人： Hitoshi Izuru ,  Kazuhiro Tashiro

IPC分类号： G01R31/26

CPC分类号： G01R31/2849

摘要： A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.

摘要翻译： 一种老化测试方法，用于在规定温度的大气中操作的半导体器件进行测试，其特征在于，在向半导体器件供电的同时，重复地提供指示半导体器件的操作的操作指令信号，并且增加和减少 对与操作指示信号相对应的电源电流进行计数。

公开(公告)号：US06462574B1

公开(公告)日：2002-10-08

申请号：US09506075

申请日：2000-02-16

申请人： Hitoshi Izuru ,  Hiroyuki Yoshioka ,  Toshiaki Tominaga

发明人： Hitoshi Izuru ,  Hiroyuki Yoshioka ,  Toshiaki Tominaga

IPC分类号： G01R3102

CPC分类号： G01R31/287

摘要： A burn-in system, a burn-in control technique, and a semiconductor device production method utilizing the burn-in control technique are provided. The burn-in system of the present invention comprises a plurality of burn-in devices and an independent counter terminal. Each of the burn-in devices calculates a parameter indicating the number of mounted semiconductor devices, and generates measurement data indicating quality of the individual semiconductor devices collectively subjected to a burn-in test. The counter terminal adds up the parameters and measurement data sent from the burn-in devices. The counter terminal then calculates a failure rate based on the total parameter and the measurement data, and stops the burn-in test of each of the burn-in devices when the failure rate reaches a predetermined reference value.

摘要翻译： 提供了老化系统，老化控制技术和利用老化控制技术的半导体器件制造方法。 本发明的老化系统包括多个老化装置和独立的计数器终端。 每个老化装置计算指示安装的半导体器件的数量的参数，并且生成表示经过老化测试的各个半导体器件的质量的测量数据。 计数器终端将从老化设备发送的参数和测量数据相加。 然后，计数器端子基于总参数和测量数据计算故障率，并且当故障率达到预定参考值时停止每个老化设备的老化测试。