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1.发明申请Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device 审中-公开半导体衬底，半导体器件的制造方法和半导体器件的测试方法公开(公告)号：US20060097356A1
公开(公告)日：2006-05-11
申请号：US11062488
申请日：2005-02-23
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.
摘要翻译： 半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。 多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。 第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。 第二划线在单元曝光和打印区域之间延伸。 第一划线的宽度与第二划线的宽度不同。
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公开(公告)号：US07915720B2
公开(公告)日：2011-03-29
申请号：US11411877
申请日：2006-04-27
申请人： Kazuhiro Tashiro , Hitoshi Izuru
发明人： Kazuhiro Tashiro , Hitoshi Izuru
IPC分类号： H01L23/02
CPC分类号： H01L22/32 , G01R31/2863 , H01L24/29 , H01L24/83 , H01L2224/16225 , H01L2224/73204 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/3011 , H01L2924/3512 , H01L2924/00
摘要： The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g. test pads 13, can be electrically connected to an external test apparatus when the semiconductor integrated circuit devices 14 and 16 are electrically connected to the circuit board 12.
摘要翻译： 本发明提供了一种高质量的半导体集成电路器件，其中半导体集成电路器件，SiP或特别是PoP半导体集成电路器件能够同时测试多个上下半导体集成电路元件的可靠性; 它还使得仅在确定有缺陷的情况下仅测试无缺陷元件; 此外，只有有缺陷的单元可与无缺陷单元交换。 本发明的半导体集成电路器件包含多个半导体集成电路元件，例如 半导体集成电路器件14和16以及中继各个半导体集成电路元件14和16以及电路板12的至少一部分的电路板12，例如， 当半导体集成电路器件14和16电连接到电路板12时，测试焊盘13可以电连接到外部测试装置。
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3.发明申请Semiconductor substrate, manufacturing method of a semiconductor device and testing method of a semiconductor device 审中-公开半导体衬底，半导体器件的制造方法和半导体器件的测试方法公开(公告)号：US20080227226A1
公开(公告)日：2008-09-18
申请号：US12153481
申请日：2008-05-20
IPC分类号： H01L21/66 , H01L21/304
CPC分类号： H01L21/78 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate eliminates a restriction caused by a width of scribe lines so as to increase a number of semiconductor elements formed on the semiconductor substrate. A plurality of semiconductor element areas are formed by forming a plurality of unit exposed and printed areas, each of which contains the semiconductor element areas. A first scribe line extends between the semiconductor element areas formed within the unit exposed and printed area. A second scribe line extends between the unit exposed and printed areas. A width of the first scribe line is different from a width of the second scribe line.
摘要翻译： 半导体衬底消除了由划线的宽度引起的限制，从而增加形成在半导体衬底上的半导体元件的数量。 多个半导体元件区域通过形成多个单位曝光和印刷区域而形成，每个单元暴露和印刷区域都包含半导体元件区域。 第一刻划线在形成在单元曝光和印刷区域内的半导体元件区域之间延伸。 第二划线在单元曝光和打印区域之间延伸。 第一划线的宽度与第二划线的宽度不同。
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公开(公告)号：US20070170425A1
公开(公告)日：2007-07-26
申请号：US11411877
申请日：2006-04-27
申请人： Kazuhiro Tashiro , Hitoshi Izuru
发明人： Kazuhiro Tashiro , Hitoshi Izuru
IPC分类号： H01L23/58
CPC分类号： H01L22/32 , G01R31/2863 , H01L24/29 , H01L24/83 , H01L2224/16225 , H01L2224/73204 , H01L2224/838 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0781 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/3011 , H01L2924/3512 , H01L2924/00
摘要： The present invention provides a high-quality semiconductor integrated circuit device, where the semiconductor integrated circuit device, a SiP or especially PoP semiconductor integrated circuit device, enables a simultaneous testing of the reliability of multiple upper and lower semiconductor integrated circuit elements; it also enables a testing of only the non-defective element in case the other is determined defective; moreover, only the defective unit is exchangeable with a non-defective unit. The semiconductor integrated circuit device of the present invention contains multiple semiconductor integrated circuit elements, e.g. semiconductor integrated circuit devices 14 and 16, and a circuit board 12 which relays the respective semiconductor integrated circuit elements 14 and 16, and at least a part of the circuit board 12, e.g. test pads 13, can be electrically connected to an external test apparatus when the semiconductor integrated circuit devices 14 and 16 are electrically connected to the circuit board 12.
摘要翻译： 本发明提供了一种高质量的半导体集成电路器件，其中半导体集成电路器件，SiP或特别是PoP半导体集成电路器件能够同时测试多个上下半导体集成电路元件的可靠性; 它还能够在另一个被确定有缺陷的情况下仅测试无缺陷元件; 此外，只有有缺陷的单元可与无缺陷单元交换。 本发明的半导体集成电路器件包含多个半导体集成电路元件，例如 半导体集成电路器件14和16以及中继各个半导体集成电路元件14和16以及电路板12的至少一部分的电路板12，例如， 当半导体集成电路器件14和16电连接到电路板12时，测试焊盘13可以电连接到外部测试装置。
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公开(公告)号：US07199600B2
公开(公告)日：2007-04-03
申请号：US11078352
申请日：2005-03-14
申请人： Hitoshi Izuru , Kazuhiro Tashiro
发明人： Hitoshi Izuru , Kazuhiro Tashiro
IPC分类号： G01R31/26
CPC分类号： G01R31/2849
摘要： A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.
摘要翻译： 一种老化测试方法，用于在规定温度的大气中操作的半导体器件进行测试，其特征在于，在向半导体器件供电的同时，重复地提供指示半导体器件的操作的操作指令信号，并且增加和减少 对与操作指示信号相对应的电源电流进行计数。
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公开(公告)号：US20060061379A1
公开(公告)日：2006-03-23
申请号：US11078352
申请日：2005-03-14
申请人： Hitoshi Izuru , Kazuhiro Tashiro
发明人： Hitoshi Izuru , Kazuhiro Tashiro
IPC分类号： G01R31/26
CPC分类号： G01R31/2849
摘要： A burn-in testing method to perform tests with a semiconductor device operated in an atmosphere at a prescribed temperature characterized in that operation instruction signals instructing an operation of the semiconductor device are repeatedly supplied while supplying power to the semiconductor device, and increases and decreases in a power supply current corresponding to the operation instruction signals are counted.
摘要翻译： 一种老化测试方法，用于在规定温度的大气中操作的半导体器件进行测试，其特征在于，在向半导体器件供电的同时，重复地提供指示半导体器件的操作的操作指令信号，并且增加和减少 对与操作指示信号相对应的电源电流进行计数。
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7.发明授权Tray in combination with electronic component attaching tool attached to the tray 失效托盘与附在托盘上的电子元件连接工具组合公开(公告)号：US08671557B2
公开(公告)日：2014-03-18
申请号：US13242647
申请日：2011-09-23
IPC分类号： B23P19/00
CPC分类号： B25B27/14 , H05K7/1061 , Y10T29/4913 , Y10T29/53174 , Y10T29/53178 , Y10T29/53183 , Y10T29/53187 , Y10T29/53191 , Y10T29/53943
摘要： A tray is provided in combination with an electronic component attaching tool attached to the tray and includes an attachment depression part that includes an inner wall and to which an electronic component is attached, wherein forming of the inner wall of the attachment depression part does not substantially depend on an external shape of the electronic component, and a standard part formed in the inner wall of the attachment depression part and engaging with a first structure part of the electronic component attaching tool to align a position of the electronic component attaching tool to the standard part when a position of the electronic component is aligned to a first position of the tray using the electronic component attaching tool, the standard part having a shape which does not substantially depend on the external shape of the electronic component.
摘要翻译： 托盘与附接到托盘上的电子部件连接工具组合地提供，并且包括附接凹陷部分，该附件凹陷部分包括内壁并且附接有电子部件，其中，附接凹陷部分的内壁的形成基本上不 取决于电子部件的外部形状，以及形成在安装凹部的内壁中的标准部分，并与电子部件安装工具的第一结构部分接合，以将电子部件安装工具的位置对准到标准 当使用电子部件安装工具将电子部件的位置与托盘的第一位置对准时，标准部件具有基本上不依赖于电子部件的外形的形状。
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公开(公告)号：US08164181B2
公开(公告)日：2012-04-24
申请号：US12872131
申请日：2010-08-31
IPC分类号： H01L23/12
CPC分类号： H01L21/67333 , H01L21/50 , H01L22/20 , H01L23/04 , H01L23/544 , H01L25/0655 , H01L2223/54473 , H01L2924/0002 , H01L2924/014 , H01L2924/15311 , H01L2924/16153 , H01L2924/1616 , H01L2924/166 , Y10T29/49826 , H01L2924/00
摘要： A semiconductor device packaging structure is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
摘要翻译： 公开了一种半导体器件封装结构，其可以提高半导体器件的性能测试的可靠性，并防止在运输或包装期间对半导体器件的损坏。 由于包含半导体芯片和具有不同高度的电气部件，所以具有高度不均匀性的半导体器件附着IC盖。 IC盖包括突出部分和基部。 在安装到半导体器件之后，突出部分位于半导体器件中的自由区域中，并且基底部分由与半导体芯片和半导体器件中的电气部件分离的突起支撑。 IC盖可拆卸地附接到半导体器件。
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9.发明申请公开(公告)号：US20110254574A1
公开(公告)日：2011-10-20
申请号：US13168719
申请日：2011-06-24
申请人： Kazuhiro Tashiro
发明人： Kazuhiro Tashiro
IPC分类号： G01R31/308 , G01R31/00 , G01N21/00 , G01R31/26
CPC分类号： G01R31/2887 , G01R31/2891
摘要： A prober includes a probe card provided with a support board and a probe attached to the support board, a stage on which a measurement wafer is mounted, a camera provided over the probe card to observe an electrode pad of a first semiconductor chip formed on the measurement wafer, and a stage moving unit for moving the position of the stage relative to the probe card.
摘要翻译： 探针包括设置有支撑板的探针卡和附接到支撑板的探针，安装有测量晶片的台，设置在探针卡上方的照相机，以观察形成在第一半导体芯片上的第一半导体芯片的电极焊盘 测量晶片和用于相对于探针卡移动台的位置的台移动单元。
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10.发明申请公开(公告)号：US20080203558A1
公开(公告)日：2008-08-28
申请号：US12081961
申请日：2008-04-24
CPC分类号： H01L21/67333 , H01L21/50 , H01L22/20 , H01L23/04 , H01L23/544 , H01L25/0655 , H01L2223/54473 , H01L2924/0002 , H01L2924/014 , H01L2924/15311 , H01L2924/16153 , H01L2924/1616 , H01L2924/166 , Y10T29/49826 , H01L2924/00
摘要： A method for protecting a semiconductor device is disclosed that can improve reliability of a performance test for the semiconductor device and prevent damage to the semiconductor device during transportation or packaging for shipment. An IC cover is attached to the semiconductor device, which has height unevenness because it includes semiconductor chips and electric parts having different heights. The IC cover includes projecting portions and a base portion. After being attached to the semiconductor device, the projecting portions stand in a free area in the semiconductor device, and the base portion is supported by the projections to be separated from the semiconductor chips and electric parts in the semiconductor device. The IC cover is detachably attached to the semiconductor device.
摘要翻译： 公开了一种用于保护半导体器件的方法，其可以提高半导体器件的性能测试的可靠性，并防止在运输或包装期间对半导体器件的损坏。 由于包含半导体芯片和具有不同高度的电气部件，所以具有高度不均匀性的半导体器件附着IC盖。 IC盖包括突出部分和基部。 在安装到半导体器件之后，突出部分位于半导体器件中的自由区域中，并且基底部分由与半导体芯片和半导体器件中的电气部件分离的突起支撑。 IC盖可拆卸地附接到半导体器件。
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