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    Data management method for memory device
    4.
    发明授权
    Data management method for memory device 失效
    存储器件的数据管理方法

    公开(公告)号：US06889287B2

    公开(公告)日：2005-05-03

    申请号：US10149552

    申请日：2001-10-12

    申请人： Junko Sasaki

    发明人： Junko Sasaki

    IPC分类号： G06F12/16 ,  G06F11/00 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/06

    CPC分类号： G06F12/0246 ,  G06F12/0292

    摘要： A data read request for a logical address Nlog is supplied from a host system to a memory apparatus. A data processing portion calculates a physical block number Nphy corresponding to the logical address Nlog using a logical-physical conversion criterion value NBASE and a logical-physical conversion multiplier NMUL of the mapping reference information. By referencing an unusable block correlation table, it is determined whether the physical block number Nphy represents an unusable block. When the physical block number Nphy represents an unusable block, a substitute block number replaces the physical block number Nphy. The data located at the physical block number Nphy or at the substitute block number is then read from a memory portion. The read data is supplied from the data processing portion to a communicating portion which supplies the read data to the host system.

    摘要翻译： 从主机系统向存储器装置提供对逻辑地址N 的数据读取请求。 数据处理部分使用逻辑 - 物理转换标准值N SUB BASE来计算与逻辑地址N＆gt; log＆lt;＆gt;相对应的物理块号码N SUB， 映射参考信息的逻辑 - 物理转换乘数N MUL 。 通过引用不可用的块相关表，确定物理块号N SUB是否表示不可用的块。 当物理块号N SUB表示不可用块时，替代块号代替物理块号N SUB phy。 然后从存储器部分读取位于物理块编号N＆gt; phy / /或替代块编号处的数据。 读取数据从数据处理部分提供给将读取的数据提供给主机系统的通信部分。

    Data memory
    5.
    发明申请
    Data memory 失效
    数据存储器

    公开(公告)号：US20050086433A1

    公开(公告)日：2005-04-21

    申请号：US10499646

    申请日：2003-10-07

    申请人： Takumi Okaue ,  Shigeo Araki ,  Junko Sasaki ,  Kenichi Nakanishi

    发明人： Takumi Okaue ,  Shigeo Araki ,  Junko Sasaki ,  Kenichi Nakanishi

    IPC分类号： G06K19/07 ,  G06F3/08 ,  G06F12/00 ,  G06F12/06 ,  G06K17/00 ,  G06K19/00 ,  G06K19/077 ,  G11C5/00

    CPC分类号： G06K19/07732 ,  G06K7/0013 ,  G06K19/072 ,  G06K19/077

    摘要： This invention provides a memory card (1) that is to be used as a storage medium in a host apparatus that can record and reproduce data. The memory card has a first memory (12-1), a second memory (12-2), a first switch (13) for changing over one memory to the other, and a second switch (14) for connecting and disconnecting an insertion/removal detecting terminal INS. The first and second switches work as a slide switch (6) provided on the housing is operated. The first switch has a contact for selecting the first memory, a contact for selecting the second memory, and a contact located between these two contacts, for selecting neither memory. The second switch connects the terminal INS to the ground while the first switch remains connected to the contact for selecting the first memory or the contact for selecting the second memory. The second switch opens the terminal INS while the first switch remains connected to the contact for selecting neither memory.

    摘要翻译： 本发明提供一种存储卡（1），其用作可以记录和再现数据的主机设备中的存储介质。 存储卡具有第一存储器（12-1），第二存储器（12-2），用于将一个存储器切换到另一存储器的第一开关（13）和用于连接和断开插入件的第二开关（14） /去除检测端子INS。 第一和第二开关的作用是设置在壳体上的滑动开关（6）。 第一开关具有用于选择第一存储器的触点，用于选择第二存储器的触点，以及位于这两个触点之间的触点，用于不选择存储器。 第二开关将端子INS连接到地，同时第一开关保持连接到触点用于选择第一存储器或用于选择第二存储器的触点。 第二开关打开端子INS，而第一开关保持连接到触点用于选择两个存储器。

    Data managing method for memory apparatus
    6.
    发明授权
    Data managing method for memory apparatus 失效

    公开(公告)号：US07296119B2

    公开(公告)日：2007-11-13

    申请号：US11115713

    申请日：2005-04-27

    申请人： Junko Sasaki

    发明人： Junko Sasaki

    IPC分类号： G06F12/06 ,  G06F11/00

    CPC分类号： G06F12/0246 ,  G06F12/0292

    摘要： A block correlation table includes block addresses of unusable block portions in an irreversibly writeable memory and includes addresses of associated substitute block portions in the irreversibly writeable memory. A request for data stored at a logical address is received from a host processor. A physical address in the irreversibly writeable memory is calculated from the logical address using a fixed mathematical relation. The physical address is compared with the block addresses in the block correlation table. When the physical address does not match any of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the physical address, and when the physical address matches one of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the address of its associated substitute block portion. The read data is transmitted to the host processor.

    Program use authorization method
    7.
    发明授权
    Program use authorization method 有权
    程序使用授权方式

    公开(公告)号：US07203958B2

    公开(公告)日：2007-04-10

    申请号：US10190735

    申请日：2002-07-09

    申请人： Hiroshi Tanaka ,  Junko Sasaki

    发明人： Hiroshi Tanaka ,  Junko Sasaki

    IPC分类号： H04L9/00

    CPC分类号： H04L9/0863 ,  H04L9/3226

    摘要： First and second codes specific to each program are prepared. The first code is encrypted to generate a first encrypted code that encrypts the second code to generate a second encrypted code. The second encrypted code is stored in a memory medium. An install key that the user needs to input is made by combining the first code and the second code. To authorize installation, the first code contained in the input install key is converted into the first encrypted code in the medium, and a computer on which a program is installed obtains the first encrypted code and generates the second encrypted code by encrypting the second code contained in the install key on the basis of the first encrypted code. Then, the computer reads out the second encrypted code stored in the medium and compares both of them, thereby giving the installation authorization.

    摘要翻译： 准备每个程序专用的第一和第二代码。 第一代码被加密以产生加密第二代码以生成第二加密代码的第一加密代码。 第二加密代码被存储在存储介质中。 通过组合第一个代码和第二个代码来完成用户需要输入的安装密钥。 要授权安装，输入安装密钥中包含的第一个代码被转换为介质中的第一个加密代码，并且安装了程序的计算机获取第一个加密代码，并通过加密第二个加密代码来生成第二个加密代码 在安装密钥的基础上第一个加密的代码。 然后，计算机读出存储在介质中的第二加密代码，并比较两者，从而给出安装授权。

    Memory device and controlling method for nonvolatile memory
    8.
    发明申请
    Memory device and controlling method for nonvolatile memory 失效
    非易失性存储器的存储器件和控制方法

    公开(公告)号：US20060047889A1

    公开(公告)日：2006-03-02

    申请号：US11207340

    申请日：2005-08-19

    申请人： Junko Sasaki ,  Kenichi Nakanishi ,  Nobuhiro Kaneko

    发明人： Junko Sasaki ,  Kenichi Nakanishi ,  Nobuhiro Kaneko

    IPC分类号： G06F12/10

    CPC分类号： G06F12/0246

    摘要： A memory device and controlling method for nonvolatile memory are provided. The memory device and the controlling method for a nonvolatile memory are provided by which, where a file management system wherein there is a tendency that lower logic addresses are used frequently like the MS-DOS is adopted, physical blocks of a flash memory are used in an averaged fashion and the life of the flash memory can be elongated thereby.

    摘要翻译： 提供了一种用于非易失性存储器的存储器件和控制方法。 提供了一种用于非易失性存储器的存储器件和控制方法，其中采用如MS-DOS那样经常使用较低逻辑地址的趋势的文件管理系统，其中使用闪速存储器的物理块 平均的时尚和闪存的使用寿命可以延长。

    Nonvolatile memory controlling method and nonvolatile memory controlling apparatus
    9.
    发明申请
    Nonvolatile memory controlling method and nonvolatile memory controlling apparatus 有权
    非易失性存储器控制方法和非易失性存储器控制装置

    公开(公告)号：US20050174857A1

    公开(公告)日：2005-08-11

    申请号：US11047723

    申请日：2005-02-02

    申请人： Takahiro Fukushige ,  Kenichi Satori ,  Kenichi Nakanishi ,  Hideaki Bando ,  Junko Sasaki ,  Kunihiko Miura ,  Toshinori Nakamura ,  Kensuke Hatsukawa

    发明人： Takahiro Fukushige ,  Kenichi Satori ,  Kenichi Nakanishi ,  Hideaki Bando ,  Junko Sasaki ,  Kunihiko Miura ,  Toshinori Nakamura ,  Kensuke Hatsukawa

    IPC分类号： G06F12/06 ,  G06F12/00 ,  G11C5/00 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G11C2216/22

    摘要： A nonvolatile-memory controlling method is disclosed which continuously accesses a plurality of memory banks structured so as to have each memory bank accessible independently. The method comprises the steps of: in a busy cycle of one of the plurality of memory banks being accessed, issuing access information to a second memory bank for access thereto; bringing the second memory bank into a selected state while the access information is being issued to the second memory bank using a selection signal for controlling a selected state and an unselected state for any one of the plurality of memory banks; bringing the memory bank in the busy cycle into an unselected state while the access information is being issued; and accessing the plurality of memory banks continuously based on the access information issued to the second memory bank in the busy cycle of one of the memory banks being accessed and in keeping with the selection signal for controlling the second memory bank.

    摘要翻译： 公开了一种非易失性存储器控制方法，其连续地访问结构化以使每个存储体可独立访问的多个存储体。 该方法包括以下步骤：在被访问的多个存储器组之一的繁忙周期中，向第二存储体发出访问信息以访问它; 当使用用于控制所选状态的选择信号和所述多个存储体中的任何一个的未选择状态向所述第二存储体发出访问信息时，使所述第二存储体进入选择状态; 在正在发出访问信息的同时，将忙碌周期中的存储器置于未选择状态; 以及基于在被访问的一个存储体组的忙周期中发送到第二存储体的访问信息并且与用于控制第二存储体的选择信号一起存取多个存储体。

    Data managing method for memory apparatus
    10.
    发明授权
    Data managing method for memory apparatus 失效
    存储装置的数据管理方法

    公开(公告)号：US07281090B2

    公开(公告)日：2007-10-09

    申请号：US11115712

    申请日：2005-04-27

    申请人： Junko Sasaki

    发明人： Junko Sasaki

    IPC分类号： G06F12/06 ,  G06F11/00

    CPC分类号： G06F12/0246 ,  G06F12/0292

    摘要： A block correlation table includes block addresses of unusable block portions in an irreversibly writeable memory and includes addresses of associated substitute block portions in the irreversibly writeable memory. A request for data stored at a logical address is received from a host processor. A physical address in the irreversibly writeable memory is calculated from the logical address using a fixed mathematical relation. The physical address is compared with the block addresses in the block correlation table. When the physical address does not match any of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the physical address, and when the physical address matches one of the block addresses in the table, the irreversibly writeable memory is referenced to read data stored at the address of its associated substitute block portion. The read data is transmitted to the host processor.

    摘要翻译： 块相关表包括不可逆写入存储器中的不可用块部分的块地址，并且包括不可逆写入存储器中相关联的替代块部分的地址。 从主处理器接收对存储在逻辑地址处的数据的请求。 使用固定数学关系从逻辑地址计算不可逆写入存储器中的物理地址。 将物理地址与块相关表中的块地址进行比较。 当物理地址与表中的任何块地址不匹配时，引用不可逆写入存储器来读取存储在物理地址中的数据，并且当物理地址与表中的块地址匹配时，不可逆写入存储器 参考存储在其相关联的替代块部分的地址处的读取数据。 读取的数据被发送到主机处理器。