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    Nonvolatile memory and method of programming the same memory
    6.
    发明授权
    Nonvolatile memory and method of programming the same memory 失效

    公开(公告)号：US07072225B2

    公开(公告)日：2006-07-04

    申请号：US11168331

    申请日：2005-06-29

    申请人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    发明人： Yoshinori Takase ,  Shoji Kubono ,  Michitaro Kanamitsu ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Hideaki Kurata

    IPC分类号： G11C16/04

    CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12

    摘要： There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

    Semiconductor integrated circuit and data processing system
    8.
    发明授权
    Semiconductor integrated circuit and data processing system 失效
    半导体集成电路和数据处理系统

    公开(公告)号：US06459621B1

    公开(公告)日：2002-10-01

    申请号：US09931030

    申请日：2001-08-17

    申请人： Takayuki Kawahara ,  Hiroshi Sato ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Satoshi Noda ,  Shoji Kubono ,  Hiroaki Kotani ,  Katsutaka Kimura

    发明人： Takayuki Kawahara ,  Hiroshi Sato ,  Atsushi Nozoe ,  Keiichi Yoshida ,  Satoshi Noda ,  Shoji Kubono ,  Hiroaki Kotani ,  Katsutaka Kimura

    IPC分类号： G11C1134

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

    摘要： A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

    摘要翻译： 闪速存储器的控制包括用于向每个非易失性存储单元提供脉冲状电压的控制，直到具有第一阈值电压的非易失性存储单元的阈值电压变为第二阈值电压为止。 控制涉及第一写入模式（粗写），其中每当施加脉冲形状电压时变化的每个非易失性存储单元的阈值电压的变化量相对变高，并且第二写入 模式（高精度写入），其中阈值电压的变化量相对低。 与高精度模式相比，改变每个存储单元的阈值电压所需的脉冲数小于粗写模式时的脉冲数。 因此，使用粗写入模式时的验证操作数量很少，因此可以加快整个写入操作。

    Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation
    9.
    发明授权
    Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation 有权
    非易失性半导体存储器包括用于提供改进的重新编程操作的控制器

    公开(公告)号：US06333871B1

    公开(公告)日：2001-12-25

    申请号：US09539634

    申请日：2000-03-30

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

    摘要翻译： 外部提供的程序数据被锁存到数据锁存电路DLL和DLR中。 在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。 与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。 基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。 即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。 即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。