公开(公告)号：US5506804A

公开(公告)日：1996-04-09

申请号：US159205

申请日：1993-11-30

申请人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

发明人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

IPC分类号： G11C11/409 ,  G05F3/24 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401

摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

公开(公告)号：US5276648A

公开(公告)日：1994-01-04

申请号：US818274

申请日：1992-01-08

申请人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

发明人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

IPC分类号： G11C11/409 ,  G05F3/24 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401

摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as current signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读取信号作为电流信号传输，然后转换为电压信号，以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

公开(公告)号：US5150325A

公开(公告)日：1992-09-22

申请号：US496227

申请日：1990-03-20

申请人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

发明人： Kazumasa Yanagisawa ,  Tatsuyuki Ohta ,  Tetsu Udagawa ,  Kyoko Ishii ,  Hitoshi Miwa ,  Atsushi Nozoe ,  Masayuki Nakamura ,  Tetsurou Matsumoto ,  Yoshitaka Kinoshita ,  Yoshiaki Ouchi ,  Hiromi Tsukada ,  Shoji Wada ,  Kazuo Mihashi ,  Yutaka Kobayashi ,  Goro Kitsukawa

IPC分类号： G11C11/409 ,  G05F3/24 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/408 ,  G11C29/00 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C29/80 ,  G11C11/4085 ,  G11C29/28 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/401

摘要： A Bi.CMOS semiconductor memory device is provided which includes an arrangement to simultaneously select a plurality of memory cells, followed by using a 3 bit Z addressing arrangement to determine a read or write operation for the simultaneously selected memory cells. To speed up the word line selection, a static selection type operation is used with the word line selecting voltage being greater than signal amplitude of the data lines during the write operation. Also, to speed up the read operation, separate common I/O lines are provided for the read and write operations. Read signals are transmitted as curent signals, and then converted to voltage signals for improving reading speed. Also, improved arrangements are provided for resistance structure, logic circuitry, input circuitry, fuse cutting circuitry, drive circuitry, power circuitry, electrostatic protection circuitry, layout structure and testing methods for the semiconductor device.

摘要翻译： 提供了一种Bi.CMOS半导体存储器件，其包括同时选择多个存储器单元的布置，随后使用3位Z寻址布置来确定对所选择的存储单元的读取或写入操作。 为了加速字线选择，在写入操作期间使用静态选择类型操作，字线选择电压大于数据线的信号幅度。 此外，为了加快读取操作，提供单独的公共I / O线用于读取和写入操作。 读信号作为固化信号传输，然后转换为电压信号以提高读取速度。 此外，为电阻结构，逻辑电路，输入电路，熔丝切割电路，驱动电路，电源电路，静电保护电路，布局结构和半导体器件的测试方法提供了改进的布置。

公开(公告)号：US5045904A

公开(公告)日：1991-09-03

申请号：US286870

申请日：1988-12-20

申请人： Yutaka Kobayashi ,  Akihiro Tanba ,  Ryoichi Hori ,  Kyoichiro Asayama ,  Seigoh Yukutake ,  Hiroyuki Miyazawa ,  Kazumasa Yanagisawa ,  Goro Kitsukawa

发明人： Yutaka Kobayashi ,  Akihiro Tanba ,  Ryoichi Hori ,  Kyoichiro Asayama ,  Seigoh Yukutake ,  Hiroyuki Miyazawa ,  Kazumasa Yanagisawa ,  Goro Kitsukawa

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/108 ,  H01L29/94

CPC分类号： H01L29/945 ,  H01L27/10829

摘要： A small and reliable semiconductor device is provided in a substrate which has an isolation trench and a capacitor trench. The isolation trench isolates a bipolar transistor from other semiconductor devices, and the capacitor trench provides capacitance to a memory cell which is formed in the substrate. The interior of the device isolation trench is kept in a floating state with respect to the surrounding semiconductor regions by forming an insulating film over the inner surface of the trench. In the capacitor trench, insulating layers and resilient conductive layers are formed alternately to form capacitance between the opposing conductive layers.

摘要翻译： 在具有隔离沟槽和电容器沟槽的衬底中提供小型且可靠的半导体器件。 隔离沟槽将双极晶体管与其它半导体器件隔离，并且电容器沟槽为在衬底中形成的存储器单元提供电容。 器件隔离沟槽的内部通过在沟槽的内表面上形成绝缘膜而相对于周围的半导体区域保持浮置状态。 在电容器沟槽中，交替地形成绝缘层和弹性导电层，以在相对的导电层之间形成电容。

公开(公告)号：US4999519A

公开(公告)日：1991-03-12

申请号：US277992

申请日：1988-11-30

申请人： Goro Kitsukawa ,  Kazumasa Yanagisawa ,  Takayuki Kawahara ,  Ryoichi Hori ,  Yoshinobu Nakagome ,  Noriyuki Hamma ,  Kiyoo Itoh ,  Hiromi Tukada

发明人： Goro Kitsukawa ,  Kazumasa Yanagisawa ,  Takayuki Kawahara ,  Ryoichi Hori ,  Yoshinobu Nakagome ,  Noriyuki Hamma ,  Kiyoo Itoh ,  Hiromi Tukada

IPC分类号： H03K19/00

CPC分类号： H03K19/0016

摘要： An ECL circuit wherein a current switch and an emitter follower are coupled, is so constructed that, in a standby mode, the current switch has its current cut off or rendered smaller than in an operating mode. In addition, the ECL circuit comprises means for decoupling a load resistance of the current switch and a base of the emitter follower in the case of cutting off the current of the current switch, or means for increasing the load resistance of the current switch in the case of rendering the current of the current switch smaller. The semiconductor circuit of the present invention can reduce the power consumption of the ECL circuit and can suppress fluctuations in the voltage levels of the outputs of the ECL circuit.

摘要翻译： 其中电流开关和射极跟随器耦合的ECL电路被构造成使得在待机模式中，电流开关的电流切断或变得比操作模式小。 此外，ECL电路包括在切断电流开关的电流的情况下解耦电流开关的负载电阻和射极跟随器的基极的装置，或用于增加电流开关的负载电阻的装置 使当前开关的电流变小的情况。 本发明的半导体电路可以降低ECL电路的功耗，并且可以抑制ECL电路的输出的电压电平的波动。

公开(公告)号：US5862095A

公开(公告)日：1999-01-19

申请号：US962351

申请日：1997-10-31

申请人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

发明人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/406

CPC分类号： G11C7/06 ,  G11C11/406

摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

摘要翻译： 普通的读/写操作（正常操作）和刷新操作彼此分离，读取的放大电路的数量或换句话说，在正常操作期间操作的读出放大器的数量小于刷新操作期间的读出放大器的数量 。 因此，可以减少正常工作期间的位线充电/放电电流。

公开(公告)号：US6108264A

公开(公告)日：2000-08-22

申请号：US234101

申请日：1999-01-19

申请人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

发明人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/406

CPC分类号： G11C7/06 ,  G11C11/406

摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

摘要翻译： 普通的读/写操作（正常操作）和刷新操作彼此分离，并且读取的放大电路的数量，或者换句话说，使得在正常操作期间操作的读出放大器的数量小于刷新期间的读出放大器的数量 操作。 因此，可以减少正常工作期间的位线充电/放电电流。

公开(公告)号：US5719815A

公开(公告)日：1998-02-17

申请号：US503738

申请日：1995-07-18

申请人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

发明人： Yasushi Takahashi ,  Takashi Shinoda ,  Masamichi Ishihara ,  Tetsu Udagawa ,  Kazumasa Yanagisawa

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C11/406

CPC分类号： G11C7/06 ,  G11C11/406

摘要： An ordinary read/write operation (normal operation) and a refresh operation are separated from one another and the number of read amplification circuits or, in other words, the number of sense amplifiers operating during the normal operation is made smaller than that during the refresh operation. Accordingly, a bit line charge/discharge current during the normal operation can be reduced.

摘要翻译： 普通的读/写操作（正常操作）和刷新操作彼此分离，并且读取的放大电路的数量，或者换句话说，使得在正常操作期间操作的读出放大器的数量小于刷新期间的读出放大器的数量 操作。 因此，可以减少正常工作期间的位线充电/放电电流。

公开(公告)号：US4807190A

公开(公告)日：1989-02-21

申请号：US17533

申请日：1987-02-24

申请人： Kyoko Ishii ,  Kazumasa Yanagisawa ,  Masaya Muranaka

发明人： Kyoko Ishii ,  Kazumasa Yanagisawa ,  Masaya Muranaka

IPC分类号： G11C11/407 ,  G11C11/408 ,  H03K5/01 ,  H03K5/02 ,  H03K17/06 ,  H03K19/096 ,  G11C7/00

CPC分类号： H03K5/023 ,  G11C11/4085

摘要： A dynamic RAM is provided in which an output voltage of a booster circuit for forming a word line selection timing signal is rendered greater than a power source potential and less than a predetermined potential by providing voltage limitation means, thereby preventing destruction of circuit elements receiving the output voltage.

摘要翻译： 提供了一种动态RAM，其中通过提供电压限制装置使用于形成字线选择定时信号的升压电路的输出电压大于电源电位并小于预定电位，从而防止接收 输出电压。

公开(公告)号：US6115319A

公开(公告)日：2000-09-05

申请号：US23880

申请日：1998-02-13

申请人： Yoshitaka Kinoshita ,  Kenji Nishimoto ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Yoshitaka Kinoshita ,  Kenji Nishimoto ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/08 ,  G11C11/401 ,  G11C11/408 ,  G11C8/18

CPC分类号： G11C11/4085 ,  G11C7/1072 ,  G11C8/08

摘要： A bootstrap circuit is provided for a word line selector for setting word lines connected with dynamic memory cells at a select level corresponding to a first voltage and a nonselect level corresponding to a second voltage. The bootstrap circuit generates a bootstrap voltage which is given a difference substantially equal to the threshold voltage of address select MOSFETs with respect to the high level of bit lines connected with the memory cells, and feeds the bootstrap voltage to the selected word lines. The bootstrap circuit is activated in synchronism with a clock signal at a timing corresponding to an action mode designated by a command in an SDRAM before a precharge action, thereby changing the select level of the word lines from the first voltage to the bootstrap voltage.

摘要翻译： 提供了一种用于字线选择器的引导电路，用于将与动态存储单元相连的字线设置在对应于与第二电压对应的第一电压和非选择电平的选择电平。 引导电路产生自举电压，该自举电压相对于与存储器单元连接的高电平位线给予基本上等于地址选择MOSFET的阈值电压的差值，并将自举电压馈送到所选择的字线。 引导电路在与预充电动作之前的SDRAM中由命令指定的动作模式对应的定时与时钟信号同步地激活，从而将字线的选择电平从第一电压改变为自举电压。