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公开(公告)号：US06248653B1
公开(公告)日：2001-06-19
申请号：US09537409
申请日：2000-03-29
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28247 , H01L29/4941
摘要： A method of manufacturing a gate structure is provided which enables to obtain a gate structure of a low resistance without increasing the height of the gate electrode, and therefore to suppress its height, by performing etching using a vapor phase hydrofluoric acid, thereby to selectively remove a TEOS oxide film (11) containing impurity at a predetermined concentration; and forming a metal film in the region surrounded by a TEOS oxide film (12) and polysilicon (3).
摘要翻译： 提供了一种制造栅极结构的方法，其通过使用气相氢氟酸进行蚀刻，能够获得低电阻的栅极结构，而不增加栅电极的高度，并因此抑制其高度，从而选择性地去除 含有预定浓度的杂质的TEOS氧化物膜（11） 在由TEOS氧化膜（12）和多晶硅（3）包围的区域内形成金属膜。
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公开(公告)号：US06521963B1
公开(公告)日：2003-02-18
申请号：US09475199
申请日：1999-12-30
IPC分类号： H01L2976
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/4983
摘要： A gate electrode (GE1) includes a polysilicon layer (4C), silicon oxide films (reoxidation films) 14, a metal layer (50C), and silicide films (15). The polysilicon layer (4C) is formed on a main surface (3BS) of a gate insulating film (3B), and the silicon oxide films (14) are formed on the side walls (4CW) of the polysilicon layer (4C). The metal layer (50C) is formed in contact with the main surface (4CS1) of the polysilicon layer (4C) on the opposite side to the gate insulating film (3B). The silicide films (15) are formed on the side walls (50CW) of the metal layer (50C) (which are composed of side walls (51CW and 52CW) of first and second metal layers (51 and 52)). After the silicide films (15) are formed, the metal layer (50C) is protected by the silicide films (15). This structure provides an MOS transistor having a polymetal gate in which oxidation of the metal layer is prevented to realize lower resistivity.
摘要翻译： 栅电极（GE1）包括多晶硅层（4C），氧化硅膜（再氧化膜）14，金属层（50C）和硅化物膜（15）。 多晶硅层（4C）形成在栅极绝缘膜（3B）的主表面（3BS）上，氧化硅膜（14）形成在多晶硅层（4C）的侧壁（4CW）上。 金属层（50C）形成为与栅极绝缘膜（3B）相反侧的多晶硅层（4C）的主表面（4CS1）接触。 硅化物膜（15）形成在金属层（50C）（由第一和第二金属层（51和52）的侧壁（51CW和52CW）构成）的侧壁（50CW）上。 在形成硅化物膜（15）之后，金属层（50C）被硅化物膜（15）保护。 该结构提供了具有多金属栅极的MOS晶体管，其中防止了金属层的氧化以实现较低的电阻率。
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3.发明授权Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer 失效在通过第一导电层的氧化形成绝缘层时，使用第二导电层作为掩模来制造栅电极的方法公开(公告)号：US06521517B1
公开(公告)日：2003-02-18
申请号：US09620138
申请日：2000-07-20
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/28247 , H01L21/32105 , H01L29/42376
摘要： A method of manufacturing a semiconductor device. The method includes forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a first conductive layer on the gate insulating film, selectively forming a second conductive layer on the first conductive layer, and selectively imparting an insulating property to the first conductive layer by using the second conductive layer as a mask, to obtain an insulating layer. The method also includes forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left when the first conductive layer was imparted the insulating property.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在第一导电类型的半导体衬底的表面上形成栅极绝缘膜，在栅极绝缘膜上形成第一导电层，在第一导电层上选择性地形成第二导电层，并选择性地赋予绝缘性 通过使用第二导电层作为掩模到第一导电层，以获得绝缘层。 该方法还包括形成与第一导电类型相反的第二导电类型的一对源极/漏极区域，以便当第一导电层被赋予绝缘体时在其间夹在其间的第一导电层下面的半导体衬底的表面 属性。
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公开(公告)号：US06335556B1
公开(公告)日：2002-01-01
申请号：US09222877
申请日：1998-12-30
IPC分类号： H01L2900
CPC分类号： H01L27/10873 , H01L21/31053 , H01L21/31612 , H01L21/31662 , H01L21/76229 , H01L27/10814 , H01L27/10894
摘要： A narrow trench (2) is formed in a memory circuit region (4) and a wide trench (200) is formed in a logic circuit region (5). An oxide (3B) is formed by CVD to fill the trench (2) and planarization is performed thereon. A thin oxide film (7) is formed by thermal oxidation in an active region, and a polysilicon (15A) for gate electrode is formed and etched only in the memory circuit region (4). At this time, the polysilicon (15B) remains in a seam (6). An oxide film (11) is deposited by CVD, to play the first role of covering the seam (6) and the second role of constituting a thick oxide film together with the oxide film (7). Thus, the trenches of different widths and the oxide films of different thicknesses are formed in a semiconductor substrate, to solve the problem of burying failure which is likely to occur in a narrow trench.
摘要翻译： 窄沟槽（2）形成在存储电路区域（4）中，宽沟槽（200）形成在逻辑电路区域（5）中。 通过CVD形成氧化物（3B）以填充沟槽（2）并在其上进行平坦化。 通过在有源区域中的热氧化形成薄氧化膜（7），并且仅在存储电路区域（4）中形成栅极电极的多晶硅（15A）并进行蚀刻。 此时，多晶硅（15B）保持在接缝（6）中。 通过CVD沉积氧化膜（11），以发挥覆盖接缝（6）的第一作用和与氧化物膜（7）一起构成厚氧化物膜的第二个作用。 因此，在半导体衬底中形成不同宽度的沟槽和不同厚度的氧化物膜，以解决在窄沟槽中容易发生的埋入故障的问题。
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公开(公告)号：US06525380B2
公开(公告)日：2003-02-25
申请号：US09324805
申请日：1999-06-03
IPC分类号： H01L2994
CPC分类号： H01L27/092 , H01L21/28176 , H01L21/823857
摘要： A semiconductor device—which includes surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film—and a manufacturing method therefor. A voltage is applied between an electrode connected to a gate electrode and an electrode connected to an N+ region formed in an n-well, and electrons are implanted into the gate electrode at high energy from a substrate, thereby producing fixed negative electric charges in a gate oxide film within an range of 1E11 cm−2 to 1E14 cm−2. An appropriate value for Vth is obtained in the surface channel MOSFET. Therefore, there are solved problems associated with a dual gate structure; namely, a complicated process flow, etch residues or excessive etching due to a difference in etch rate between n-type polycrystalline silicon and p-type polycrystalline silicon, and the deterioration of a gate oxide film due to penetration of boron ions.
摘要翻译： 一种半导体器件及其制造方法，其包括在栅极氧化膜内形成固定电荷的表面型n沟道和p沟道单栅极晶体管。 在连接到栅电极的电极和连接到形成在n阱中的N +区域的电极之间施加电压，并且电子以高能量从衬底注入到栅电极中，从而在电极中产生固定的负电荷 栅极氧化膜在1E11cm-2至1E14cm-2的范围内。 在表面沟道MOSFET中获得适当的Vth值。 因此，解决了与双栅结构相关的问题; 即由于n型多晶硅和p型多晶硅之间的蚀刻速率差异导致的复杂工艺流程，蚀刻残留物或过度蚀刻以及由于硼离子渗透导致的栅极氧化膜的劣化。
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公开(公告)号：US06333222B1
公开(公告)日：2001-12-25
申请号：US09399369
申请日：1999-09-20
IPC分类号： H01L218244
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.
摘要翻译： 在制造DRAM混合逻辑存储器的方法中，首先形成一个栅电极的图形，然后形成另一个栅电极的图形。 此后进行氧化多晶硅残渣的步骤。 因此，防止多晶硅渣残留，并且防止电气短路。
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公开(公告)号：US20070204681A1
公开(公告)日：2007-09-06
申请号：US11710974
申请日：2007-02-27
CPC分类号： G01Q70/12 , C12N15/89 , G01Q60/54 , Y10S977/86 , Y10S977/863 , Y10S977/875 , Y10S977/876 , Y10S977/879
摘要： A carbon thin line probe having a carbon thin line selectively formed at a projection-like terminal end portion thereof by means of an irradiation of high-energy beam, the carbon thin line internally containing a metal. Thereby achieved is a carbon thin line probe suitable for example for the probe of SPM cantilever, which has a high aspect ratio and high durability and reliability, capability of batch processing based on a simple manufacturing method, and to which magnetic characteristic can be imparted.
摘要翻译： 一种碳细线探针，其具有通过高能束的照射在其突起状端部选择性地形成的碳细线，所述碳细线在内部含有金属。 由此实现了适用于例如SPM悬臂的探针的碳细线探针，其具有高纵横比和高耐久性和可靠性，基于简单制造方法的批处理能力，并且可赋予其磁特性。
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公开(公告)号：US20080121029A1
公开(公告)日：2008-05-29
申请号：US12007615
申请日：2008-01-14
申请人： Masashi Kitazawa , Junpei Yoneyama
发明人： Masashi Kitazawa , Junpei Yoneyama
IPC分类号： G01N13/16
摘要： A cantilever having a support portion, a lever portion extended from the support portion, and a probe portion formed in the vicinity of a free end of the lever portion, in which a carbon nano-tube controlled in direction is attached to the probe portion in a manner jutting out from a terminal end portion of the probe portion.
摘要翻译： 具有支撑部的悬臂，从所述支撑部延伸的杆部，以及形成在所述杆部的自由端附近的探针部，所述探针部在所述杆部的自由端附近以将所述方向控制的碳纳米管附接到所述探针部的方式 从探针部的末端部突出的方式。
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公开(公告)号：US20070241373A1
公开(公告)日：2007-10-18
申请号：US11577878
申请日：2005-10-18
IPC分类号： H01L29/768 , H01L21/76 , H01L29/00
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.
摘要翻译： 在制造半导体器件的过程中，在衬底上形成第一层，并且蚀刻第一层和衬底以形成沟槽。 沟槽的内壁被热氧化。 在包括沟槽内部的衬底上沉积厚度等于或大于沟槽宽度的一半的第一导电膜。 通过化学机械抛光去除第一层上的第一导电膜，使得第一导电膜仅保留在沟槽中。 通过各向异性蚀刻第一导电膜，将沟槽中的第一导电膜的高度调节为低于衬底的表面。 通过化学气相沉积在衬底上沉积绝缘膜以覆盖沟槽中的第一导电膜的上表面。 绝缘膜通过化学机械抛光而变平，第一层被去除。
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公开(公告)号：US07010966B2
公开(公告)日：2006-03-14
申请号：US10694358
申请日：2003-10-28
申请人： Masashi Kitazawa , Koichi Shiotani , Akitoshi Toda
发明人： Masashi Kitazawa , Koichi Shiotani , Akitoshi Toda
IPC分类号： G01B5/28
摘要： Disclosed herein is SPM cantilever having a support portion, a lever portion extended from the support portion and a probe portion formed at a free end of the lever portion, said probe portion having a generally plate-like form and the probe portion having an additionally sharpened terminal end portion. The terminal end portion has its length greater than the plate thickness thereof and is reduced in thickness toward a tip of the terminal end portion, and the tip is located inwardly of the planes extended from the front and back sides of a base portion of the plate-like probe portion.
摘要翻译： 本文公开了具有支撑部分的SPM悬臂，从支撑部分延伸的杆部分和形成在杠杆部分的自由端的探针部分，所述探针部分具有大致板形的形状，并且探针部分具有另外锋利的 末端部。 终端部的长度大于其板厚，并且朝向终端部的前端减小，并且该端部位于从板的基部的前后侧延伸的平面的内侧 样的探针部分。
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