-
公开(公告)号：US06335556B1
公开(公告)日：2002-01-01
申请号：US09222877
申请日：1998-12-30
IPC分类号： H01L2900
CPC分类号： H01L27/10873 , H01L21/31053 , H01L21/31612 , H01L21/31662 , H01L21/76229 , H01L27/10814 , H01L27/10894
摘要： A narrow trench (2) is formed in a memory circuit region (4) and a wide trench (200) is formed in a logic circuit region (5). An oxide (3B) is formed by CVD to fill the trench (2) and planarization is performed thereon. A thin oxide film (7) is formed by thermal oxidation in an active region, and a polysilicon (15A) for gate electrode is formed and etched only in the memory circuit region (4). At this time, the polysilicon (15B) remains in a seam (6). An oxide film (11) is deposited by CVD, to play the first role of covering the seam (6) and the second role of constituting a thick oxide film together with the oxide film (7). Thus, the trenches of different widths and the oxide films of different thicknesses are formed in a semiconductor substrate, to solve the problem of burying failure which is likely to occur in a narrow trench.
摘要翻译： 窄沟槽（2）形成在存储电路区域（4）中，宽沟槽（200）形成在逻辑电路区域（5）中。 通过CVD形成氧化物（3B）以填充沟槽（2）并在其上进行平坦化。 通过在有源区域中的热氧化形成薄氧化膜（7），并且仅在存储电路区域（4）中形成栅极电极的多晶硅（15A）并进行蚀刻。 此时，多晶硅（15B）保持在接缝（6）中。 通过CVD沉积氧化膜（11），以发挥覆盖接缝（6）的第一作用和与氧化物膜（7）一起构成厚氧化物膜的第二个作用。 因此，在半导体衬底中形成不同宽度的沟槽和不同厚度的氧化物膜，以解决在窄沟槽中容易发生的埋入故障的问题。
-
公开(公告)号：US06525380B2
公开(公告)日：2003-02-25
申请号：US09324805
申请日：1999-06-03
IPC分类号： H01L2994
CPC分类号： H01L27/092 , H01L21/28176 , H01L21/823857
摘要： A semiconductor device—which includes surface-type n-channel and p-channel single gate transistors by formation of fixed charges within a gate oxide film—and a manufacturing method therefor. A voltage is applied between an electrode connected to a gate electrode and an electrode connected to an N+ region formed in an n-well, and electrons are implanted into the gate electrode at high energy from a substrate, thereby producing fixed negative electric charges in a gate oxide film within an range of 1E11 cm−2 to 1E14 cm−2. An appropriate value for Vth is obtained in the surface channel MOSFET. Therefore, there are solved problems associated with a dual gate structure; namely, a complicated process flow, etch residues or excessive etching due to a difference in etch rate between n-type polycrystalline silicon and p-type polycrystalline silicon, and the deterioration of a gate oxide film due to penetration of boron ions.
摘要翻译： 一种半导体器件及其制造方法，其包括在栅极氧化膜内形成固定电荷的表面型n沟道和p沟道单栅极晶体管。 在连接到栅电极的电极和连接到形成在n阱中的N +区域的电极之间施加电压，并且电子以高能量从衬底注入到栅电极中，从而在电极中产生固定的负电荷 栅极氧化膜在1E11cm-2至1E14cm-2的范围内。 在表面沟道MOSFET中获得适当的Vth值。 因此，解决了与双栅结构相关的问题; 即由于n型多晶硅和p型多晶硅之间的蚀刻速率差异导致的复杂工艺流程，蚀刻残留物或过度蚀刻以及由于硼离子渗透导致的栅极氧化膜的劣化。
-
公开(公告)号：US06521963B1
公开(公告)日：2003-02-18
申请号：US09475199
申请日：1999-12-30
IPC分类号： H01L2976
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/4983
摘要： A gate electrode (GE1) includes a polysilicon layer (4C), silicon oxide films (reoxidation films) 14, a metal layer (50C), and silicide films (15). The polysilicon layer (4C) is formed on a main surface (3BS) of a gate insulating film (3B), and the silicon oxide films (14) are formed on the side walls (4CW) of the polysilicon layer (4C). The metal layer (50C) is formed in contact with the main surface (4CS1) of the polysilicon layer (4C) on the opposite side to the gate insulating film (3B). The silicide films (15) are formed on the side walls (50CW) of the metal layer (50C) (which are composed of side walls (51CW and 52CW) of first and second metal layers (51 and 52)). After the silicide films (15) are formed, the metal layer (50C) is protected by the silicide films (15). This structure provides an MOS transistor having a polymetal gate in which oxidation of the metal layer is prevented to realize lower resistivity.
摘要翻译： 栅电极（GE1）包括多晶硅层（4C），氧化硅膜（再氧化膜）14，金属层（50C）和硅化物膜（15）。 多晶硅层（4C）形成在栅极绝缘膜（3B）的主表面（3BS）上，氧化硅膜（14）形成在多晶硅层（4C）的侧壁（4CW）上。 金属层（50C）形成为与栅极绝缘膜（3B）相反侧的多晶硅层（4C）的主表面（4CS1）接触。 硅化物膜（15）形成在金属层（50C）（由第一和第二金属层（51和52）的侧壁（51CW和52CW）构成）的侧壁（50CW）上。 在形成硅化物膜（15）之后，金属层（50C）被硅化物膜（15）保护。 该结构提供了具有多金属栅极的MOS晶体管，其中防止了金属层的氧化以实现较低的电阻率。
-
4.发明授权Method of fabricating a gate electrode using a second conductive layer as a mask in the formation of an insulating layer by oxidation of a first conductive layer 失效在通过第一导电层的氧化形成绝缘层时，使用第二导电层作为掩模来制造栅电极的方法公开(公告)号：US06521517B1
公开(公告)日：2003-02-18
申请号：US09620138
申请日：2000-07-20
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/28247 , H01L21/32105 , H01L29/42376
摘要： A method of manufacturing a semiconductor device. The method includes forming a gate insulating film on a surface of a semiconductor substrate of a first conductivity type, forming a first conductive layer on the gate insulating film, selectively forming a second conductive layer on the first conductive layer, and selectively imparting an insulating property to the first conductive layer by using the second conductive layer as a mask, to obtain an insulating layer. The method also includes forming a pair of source/drain regions of a second conductivity type opposite to the first conductivity type, so as to sandwich therebetween the surface of the semiconductor substrate underlying the first conductive layer left when the first conductive layer was imparted the insulating property.
摘要翻译： 一种制造半导体器件的方法。 该方法包括在第一导电类型的半导体衬底的表面上形成栅极绝缘膜，在栅极绝缘膜上形成第一导电层，在第一导电层上选择性地形成第二导电层，并选择性地赋予绝缘性 通过使用第二导电层作为掩模到第一导电层，以获得绝缘层。 该方法还包括形成与第一导电类型相反的第二导电类型的一对源极/漏极区域，以便当第一导电层被赋予绝缘体时在其间夹在其间的第一导电层下面的半导体衬底的表面 属性。
-
公开(公告)号：US06333222B1
公开(公告)日：2001-12-25
申请号：US09399369
申请日：1999-09-20
IPC分类号： H01L218244
CPC分类号： H01L27/10894 , H01L27/105 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： In the method of manufacturing the DRAM mixed logic memory, first, a pattern of one gate electrode is formed, and then a pattern of another gate electrode is formed. A step of oxidizing a polycrystalline silicon residue is performed thereafter. Therefore, the polycrystalline silicon residue is prevented from being left and prevention of electric short circuit is allowed.
摘要翻译： 在制造DRAM混合逻辑存储器的方法中，首先形成一个栅电极的图形，然后形成另一个栅电极的图形。 此后进行氧化多晶硅残渣的步骤。 因此，防止多晶硅渣残留，并且防止电气短路。
-
公开(公告)号：US06248653B1
公开(公告)日：2001-06-19
申请号：US09537409
申请日：2000-03-29
IPC分类号： H01L213205
CPC分类号： H01L29/66545 , H01L21/28061 , H01L21/28247 , H01L29/4941
摘要： A method of manufacturing a gate structure is provided which enables to obtain a gate structure of a low resistance without increasing the height of the gate electrode, and therefore to suppress its height, by performing etching using a vapor phase hydrofluoric acid, thereby to selectively remove a TEOS oxide film (11) containing impurity at a predetermined concentration; and forming a metal film in the region surrounded by a TEOS oxide film (12) and polysilicon (3).
摘要翻译： 提供了一种制造栅极结构的方法，其通过使用气相氢氟酸进行蚀刻，能够获得低电阻的栅极结构，而不增加栅电极的高度，并因此抑制其高度，从而选择性地去除 含有预定浓度的杂质的TEOS氧化物膜（11） 在由TEOS氧化膜（12）和多晶硅（3）包围的区域内形成金属膜。
-
公开(公告)号：US06461920B1
公开(公告)日：2002-10-08
申请号：US09654877
申请日：2000-09-05
IPC分类号： H01L218236
CPC分类号： H01L21/26513 , H01L21/74 , H01L27/088 , H01L29/105
摘要： In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.
摘要翻译： 在半导体器件中，在半导体衬底的主表面上形成具有不同阈值的相同导电类型的多个MIS晶体管，并且在深度方向上从半导体衬底的主表面延伸通过各个沟道区域 多个MIS晶体管的峰值位于不同深度处。 该结构通过在具有不同注入能量或不同离子种类的各个沟道区上进行的离子注入形成。 根据该半导体器件，可以单独地控制MIS晶体管的阈值，并且可以获得对于使用最佳的晶体管特性。
-
8.发明授权
公开(公告)号：US5683923A
公开(公告)日：1997-11-04
申请号：US480701
申请日：1995-06-07
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/265
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5. Therefore, an electric field, which is generated across the floating gate electrode 5 and the drain diffusion region 9 in an unselected cell during writing of data, is weakened, as compared with the prior art, and the drain disturb phenomenon due to F-N tunneling is effectively prevented.
摘要翻译： 半导体存储器件及其制造方法可以有效地防止在数据擦除操作中可能发生的耐久特性的劣化，以及在数据写入操作中可能发生的漏极干扰现象。 在半导体存储器件中，在位于沟道区域中的P型硅衬底1的主表面上形成N型杂质层3。 因此，在擦除数据期间，不向N型杂质层3和N型源极扩散区域10之间的边界区域施加高电场，从而有效地防止了在该区域产生带间隧穿。 另外，在该半导体存储器件中，漏极扩散区域9具有偏移结构，其中没有任何部分与浮置栅极电极5重叠。因此，在浮置栅极电极5和漏极扩散区域9两端产生的电场 与现有技术相比，写入数据期间的未选择的单元被削弱，并且有效地防止了由于FN隧穿引起的漏极干扰现象。
-
公开(公告)号：US06555887B1
公开(公告)日：2003-04-29
申请号：US09368345
申请日：1999-08-05
IPC分类号： H01L31119
CPC分类号： H01L21/76886 , H01L21/28061 , H01L21/76801 , H01L21/76838
摘要： A semiconductor device with a polycide interconnection including a refractory metal silicide film improved in adherence with an interlayer insulation film, and a method of fabricating such a semiconductor device are provided. The local impurity concentration of a tungsten silicide film in the proximity of the interface between an interlayer oxide film and the tungsten silicide film is set to 5×1019 atms/cm3-2×1022 atms/cm3.
摘要翻译： 提供了具有提高了与层间绝缘膜的粘附性的难熔金属硅化物膜的具有多晶硅互连的半导体器件，以及制造这种半导体器件的方法。 在层间氧化膜和硅化钨膜之间的界面附近的硅化钨膜的局部杂质浓度设定为5×1019atms / cm 2 -2×10 22 atms / cm 3。
-
公开(公告)号：US6144079A
公开(公告)日：2000-11-07
申请号：US725386
申请日：1996-10-03
IPC分类号： H01L21/336 , H01L21/265 , H01L21/74 , H01L21/8238 , H01L27/088 , H01L27/092 , H01L29/10 , H01L29/78 , H01L31/119 , H01L27/119 , H01L29/76 , H01L27/108
CPC分类号： H01L29/105 , H01L21/26513 , H01L21/74 , H01L27/088
摘要： In a semiconductor device, a plurality of MIS transistors of the same conductivity type having different thresholds are formed at a main surface of semiconductor substrate, and impurity profiles on section extending in a depth direction from the main surface of the semiconductor substrate through respective channel regions of the plurality of MIS transistors have peaks located at different depths. This structure is formed by ion implantation performed on the respective channel regions with different implanting energies or different ion species. According to this semiconductor device, the thresholds of the MIS transistors can be individually controlled, and transistor characteristics optimum for uses can be obtained.
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.018 秒)
