公开(公告)号：US5831903A

公开(公告)日：1998-11-03

申请号：US868138

申请日：1997-06-03

申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。 每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。 存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。 当在数据编程模式中将数据一次写入所选择的存储单元中时，将特定的基准电压施加到所选择的单元，以便验证所选存储单元的实际电数据写入条件。 如果比较器检测到验证的写入条件不满意，则通过用选择的存储单元晶体管补偿所验证的写入条件的不满足的适当电压来额外提供所选择的单元来重复执行数据重写操作。

公开(公告)号：US5657270A

公开(公告)日：1997-08-12

申请号：US376665

申请日：1995-01-23

申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including a plurality of bit lines; a plurality of word lines insulatively intersecting the bit lines; a memory cell array including a plurality of memory cells coupled to the bit lines and the word lines, each memory cell including a transistor with a charge storage portion; a plurality of programming circuits coupled to the memory cell array (i) for storing data which define whether or not write voltages are to be applied to respective of the memory cells, (ii) for selectively applying the write voltages to a part of the memory cells, which part is selected according to the data stored in the plurality of programing circuits, (iii) for determining actual written states of the memory cells, and (iv) for selectively modifying the stored data based on a predetermined logical relationship between the determined actual written states of the memory cells and the data stored in the plurality of programming circuits, thereby applying the write voltages only to memory cells which are not sufficiently written to achieve a predetermined written state.

摘要翻译： 一种包括多个位线的非易失性半导体存储器件; 多个字线与位线绝对相交; 包括耦合到位线和字线的多个存储单元的存储单元阵列，每个存储单元包括具有电荷存储部分的晶体管; 耦合到存储单元阵列（i）的多个编程电路，用于存储定义是否将写入电压施加到存储单元的相应数据的数据，（ii）用于选择性地将写入电压施加到存储器的一部分 单元，根据存储在多个编程电路中的数据选择该部分，（iii）用于确定存储单元的实际写入状态，以及（iv）基于所确定的预定逻辑关系来选择性地修改所存储的数据 存储单元的实际写入状态和存储在多个编程电路中的数据，从而将写入电压仅施加到未被充分写入以实现预定写入状态的存储单元。

公开(公告)号：US6081454A

公开(公告)日：2000-06-27

申请号：US145466

申请日：1998-09-02

申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。 每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。 存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。 当在数据编程模式下将数据一次写入所选择的存储单元中时，将特定的偏置电压施加到所选择的单元，从而验证所选存储单元的实际电数据写入状态。 如果比较器检测到验证的写入条件不满意，则通过向所选择的单元格额外提供补偿所选择的存储单元晶体管中的验证的写入条件的不满足的适当电压来重复执行数据重写操作。

公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US5247480A

公开(公告)日：1993-09-21

申请号：US773723

申请日：1991-10-09

申请人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

发明人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

摘要： An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.

摘要翻译： 电可擦除可编程只读存储器具有存储单元块，每个存储单元块分别具有与位线相关联的NAND型单元单元。 每个单元单元具有浮置型存储单元晶体管的串联电路和设置在相应位线和存储单元晶体管的串联电路之间的选择晶体管。 向存储单元块共同地提供行解码器，用于产生提供给连接到选择晶体管的选择栅极控制线和单元单元中所选择的字线或线的“H”电平电压。 为每个存储单元块提供升压电路，用于使“H”电平电压增加到足以使单元晶体管导通的预选电位电平。 升压电路包括用于选择栅极控制线的第一升压部分和用于字线的第二部分。 第二部分响应于第一部分的输出电压而工作。

公开(公告)号：US5179427A

公开(公告)日：1993-01-12

申请号：US869123

申请日：1992-04-15

申请人： Ryozo Nakayama ,  Riichiro Shirota ,  Yasuo Itoh ,  Ryouhei Kirisawa ,  Hideko Odaira ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Seiichi Aritome ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Ryozo Nakayama ,  Riichiro Shirota ,  Yasuo Itoh ,  Ryouhei Kirisawa ,  Hideko Odaira ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Seiichi Aritome ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0483

摘要： A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.

摘要翻译： NAND单元型EEPROM具有形成在衬底上的并行数据传输线，以及存储单元部分，其包括与位线的某个位线相关联的NAND型单元单元的多个NAND型单元单元。 该NAND型单元单元具有预选数量的具有控制栅极的数据存储晶体管和选择晶体管的串联电路。 衬底电压稳定层被绝缘地设置在衬底之上并且位于与某一位线相邻的场区中。 导电层通过接触部分连接到基板，使得在对NAND型单元单元进行写入和擦除模式期间，基板电压可以恒定地设定为固定值的预选电压电位。

公开(公告)号：US5075890A

公开(公告)日：1991-12-24

申请号：US516311

申请日：1990-04-30

申请人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

发明人： Yasuo Itoh ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Fujio Masuoka

IPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

CPC分类号： G11C16/08 ,  G11C16/12 ,  G11C16/30

摘要： An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.

摘要翻译： 电可擦除可编程只读存储器具有存储单元块，每个存储单元块分别具有与位线相关联的NAND型单元单元。 每个单元单元具有浮置型存储单元晶体管的串联电路和设置在相应位线和存储单元晶体管的串联电路之间的选择晶体管。 向存储单元块共同地提供行解码器，用于产生提供给连接到选择晶体管的选择栅极控制线和单元单元中所选择的字线或线的“H”电平电压。 为每个存储器单元块提供升压电路，用于使“H”电平电压增加到足以使单元晶体管导通的预选电位电平。 升压电路包括用于选择栅极控制线的第一升压部分和用于字线的第二部分。 第二部分响应于第一部分的输出电压而工作。

公开(公告)号：USRE35838E

公开(公告)日：1998-07-07

申请号：US430271

申请日：1995-04-28

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

IPC分类号： G11C16/16 ,  G11C17/00

CPC分类号： G11C16/16

摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其具有设置在N型衬底上的存储单元。 存储器单元被分成NAND单元块，每个单元块具有存储单元晶体管的串联阵列。 每个晶体管具有浮置栅极，连接到字线的控制栅极和用作其源极和漏极的N型扩散层。 这些半导体层形成在形成于基板的表面区域的P型阱层中。 阱层用作表面击穿防止层。 在数据擦除模式期间，存储在所有存储单元中的数据同时被擦除。 在擦除模式之后的数据写入模式期间，当选择某个NAND单元块时，NAND单元块中的存储单元依次进行数据写入。 当数据被写入所选择的NAND单元块中的某个存储单元中时，该特定存储单元的控制栅极被提供有如此高的电压，以形成强电场，以允许在浮置栅极 的存储单元和阱层。 因此，只能选择所选单元格。

公开(公告)号：US4959812A

公开(公告)日：1990-09-25

申请号：US289702

申请日：1988-12-27

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Riichiro Shirota ,  Yasuo Itoh ,  Kazunori Ohuchi ,  Ryouhei Kirisawa

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/16 ,  G11C16/0483

摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a control gate connected to a word line and N type diffusion layers serving as its source and drain. These semiconductor layers are formed in a P type well layer formed in a surface area of a substrate. The well layer serves as a surface breakdown prevention layer. During a data erase mode data stored in all the memory cells are erased simultaneously. During the data write mode subsequent to the erase mode, when a certain NAND cell block is selected, memory cells in the NAND cell block are subjected to data writing in sequence. When data is written into a certain memory cell in the selected NAND cell block, a control gate of the certain memory cell is supplied with a voltage which is so high as to form a strong electric field to allow the tunneling of electrons between the floating gate of the memory cell and the well layer. Consequently, only the selected cell can be written into.

公开(公告)号：US5400279A

公开(公告)日：1995-03-21

申请号：US67005

申请日：1993-05-26

申请人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba

发明人： Masaki Momodomi ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Fujio Masuoka ,  Masahiko Chiba

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C7/00

CPC分类号： G11C16/32 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

摘要： An electrically erasable programmable read-only memory has an array of programmable memory cells connected to parallel bit lines on a semiconductive substrate. The memory cells include NAND cell blocks each of which has a first selection transistor coupled to a corresponding bit line, a second selection transistor coupled to the ground potential, and a series array of memory cell transistors each having a floating gate and a control gate. Word lines are respectively connected to the control gates of the memory cell transistors. In a data read mode, a selection transistor of a certain NAND cell block including a selected memory cell transistor is rendered conductive to connect this cell block to a bit line associated therewith. Under such a condition, a low or "L" level voltage is applied by a row decoder & bootstrap circuit section to a word line connected to the selected memory cell transistor, and a pulse voltage signal having a high or "H" level is supplied by the row decoder & bootstrap circuit section to the remaining word lines, so that data stored in the selected memory cell is read out. The "H" level of the voltage signal is higher than the power supply voltage and yet lower than a normal "H" level used in data write and erase modes. The pulse width of the pulse voltage signal is shorter than the period of one read cycle.

摘要翻译： 电可擦除可编程只读存储器具有连接到半导体衬底上的并行位线的可编程存储器单元阵列。 存储器单元包括NAND单元块，每个NAND单元块具有耦合到对应位线的第一选择晶体管，耦合到地电位的第二选择晶体管，以及每个具有浮置栅极和控制栅极的存储单元晶体管的串联阵列。 字线分别连接到存储单元晶体管的控制栅极。 在数据读取模式中，将包括所选存储单元晶体管的某个NAND单元块的选择晶体管导通，以将该单元块连接到与其相关联的位线。 在这种情况下，由行解码器和自举电路部分将低电平或“L”电平施加到连接到所选择的存储单元晶体管的字线，并且提供具有高或“H”电平的脉冲电压信号 通过行解码器和引导电路部分到剩余的字线，使得读出存储在所选存储单元中的数据。 电压信号的“H”电平高于电源电压，但低于在数据写入和擦除模式下使用的正常“H”电平。 脉冲电压信号的脉冲宽度比一个读周期的周期短。