公开(公告)号：US5179427A

公开(公告)日：1993-01-12

申请号：US869123

申请日：1992-04-15

申请人： Ryozo Nakayama ,  Riichiro Shirota ,  Yasuo Itoh ,  Ryouhei Kirisawa ,  Hideko Odaira ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Seiichi Aritome ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Ryozo Nakayama ,  Riichiro Shirota ,  Yasuo Itoh ,  Ryouhei Kirisawa ,  Hideko Odaira ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Tomoharu Tanaka ,  Seiichi Aritome ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0483

摘要： A NAND cell type EEPROM has parallel data transmission lines formed above a substrate, and a memory cell section including a plurality of NAND type cell units containing a NAND type cell unit that is associated with a certain bit line of the bit lines. This NAND type cell unit has a series-circuit of a preselected number of data storage transistors with control gates, and a selection transistor. A substrate voltage-stabilizing layer is insulatively provided above the substrate and positioned in the field area in adjacent to the certain bit line. The conductive layer is connected to the substrate by a contact portion so that the substrate voltage can be constantly set to a preselected voltage potential of a fixed value during the NAND type cell unit is being subjected to the write and erase modes.

摘要翻译： NAND单元型EEPROM具有形成在衬底上的并行数据传输线，以及存储单元部分，其包括与位线的某个位线相关联的NAND型单元单元的多个NAND型单元单元。 该NAND型单元单元具有预选数量的具有控制栅极的数据存储晶体管和选择晶体管的串联电路。 衬底电压稳定层被绝缘地设置在衬底之上并且位于与某一位线相邻的场区中。 导电层通过接触部分连接到基板，使得在对NAND型单元单元进行写入和擦除模式期间，基板电压可以恒定地设定为固定值的预选电压电位。

公开(公告)号：US5978265A

公开(公告)日：1999-11-02

申请号：US746176

申请日：1991-08-15

申请人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

发明人： Ryouhei Kirisawa ,  Riichiro Shirota ,  Ryozo Nakayama ,  Seiichi Aritome ,  Masaki Momodomi ,  Yasuo Itoh ,  Fujio Masuoka

IPC分类号： G11C17/12 ,  G11C16/04 ,  G11C16/10 ,  G11C17/00 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： An electrically erasable programmable read-only memory is disclosed which has programmable memory cells connected to parallel bit lines provided above a semiconductor substrate. The memory cells include NAND cell blocks each of which has a series array of memory cell transistors. Parallel word lines are connected to the control gates of the memory cell transistors, respectively. In a data write mode, a selection transistor in a certain NAND cell block including a selected memory cell is rendered conductive to connect the certain cell block to a corresponding bit line associated therewith. Under such a condition, electrons are tunnel-injected into a floating gate of the selected memory cell transistor, and the threshold value of the certain transistor is increased to be a positive value. A logical data is thus written in the selected memory cell transistor. The data in the selected cell transistor is erased by discharging carriers accumulated in the floating gate thereof to its drain or the substrate, so that the threshold value of the certain transistor is decreased to be a negative value.

摘要翻译： 公开了一种电可擦除可编程只读存储器，其具有连接到设置在半导体衬底上的并行位线的可编程存储器单元。 存储单元包括NAND单元块，每个NAND单元具有存储单元晶体管的串联阵列。 并行字线分别连接到存储单元晶体管的控制栅极。 在数据写入模式中，包括所选择的存储单元的某个NAND单元块中的选择晶体管被导通以将特定单元块连接到与其相关联的相应位线。 在这种条件下，电子被隧道注入到所选择的存储单元晶体管的浮动栅极中，并且特定晶体管的阈值增加到正值。 因此，逻辑数据被写入所选择的存储单元晶体管中。 通过将其浮置栅极中累积的载流子放电到其漏极或衬底来擦除所选择的单元晶体管中的数据，使得某个晶体管的阈值降低为负值。

公开(公告)号：US5508957A

公开(公告)日：1996-04-16

申请号：US312072

申请日：1994-09-26

申请人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Fujio Masuoka ,  Yasuo Itoh ,  Hiroshi Iwahashi ,  Yoshihisa Iwata ,  Masahiko Chiba ,  Satoshi Inoue ,  Riichiro Shirota ,  Ryozo Nakayama ,  Kazunori Ohuchi ,  Shigeyoshi Watanabe ,  Ryouhei Kirisawa

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  H01L27/115 ,  G11C16/06 ,  H01L29/788

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  H01L27/115

摘要： An erasable programmable read-only memory with NAND cell structure includes NAND cell blocks, each of which has a selection transistor connected to the corresponding bit line and a series array of memory cell transistors, and a switching transistor connected between the series array of memory cell transistors and ground. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data writing mode, a selection transistor of a certain cell block containing a selected cell is rendered conductive, so that this cell block is connected to the corresponding bit line. Under such a condition, a decoder circuit stores a desired data (a logic "one" e.g.) in the selected cell, by applying an "H" level voltage to the bit line, applying an "L" level voltage to a word line connected to the selected cell, applying the "H" level voltage to a memory cell or cells positioned between the selected cell and the bit line, and applying the "L" level voltage to a memory cell or cells positioned between the selected cell and the ground. The selection transistor and switching transistor for a corresponding series array of memory cell transistors have different channel lengths to reduce punch through.

摘要翻译： 具有NAND单元结构的可擦除可编程只读存储器包括NAND单元块，每个单元块具有连接到对应位线的选择晶体管和存储单元晶体管的串联阵列，以及连接在串联阵列存储单元之间的开关晶体管 晶体管和地。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据写入模式中，包含所选择的单元的某个单元块的选择晶体管被导通，使得该单元块连接到对应的位线。 在这种情况下，解码器电路通过向位线施加“H”电平电压，将所需数据（例如逻辑“1”）存储在所选择的单元中，对连接的字线施加“L”电平电压 将“H”电平施加到位于所选择的单元和位线之间的存储单元或单元，并将“L”电平施加到位于所选单元和地之间的存储单元或单元 。 用于存储单元晶体管的相应串联阵列的选择晶体管和开关晶体管具有不同的沟道长度以减少穿通。

公开(公告)号：US4939690A

公开(公告)日：1990-07-03

申请号：US290427

申请日：1988-12-27

申请人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

发明人： Masaki Momodomi ,  Riichiro Shirota ,  Yasuo Itoh ,  Satoshi Inoue ,  Fujio Masuoka ,  Ryozo Nakayama ,  Ryouhei Kirisawa

IPC分类号： G11C16/04

CPC分类号： G11C16/0483

摘要： An erasable programmable read-only memory with NAND cell structure is disclosed which includes NAND cell blocks each of which has a selection transistor connected to a corresponding bit line and a series array of memory cell transistors. Each cell transistor has a floating gate and a control gate. Word lines are connected to the control gates of the cell transistors. In a data erase mode all the memory cells are simultaneously erased by applying a "H" level potential to the control gates of the memory cells and a "L" level potential to the bit lines. Prior to such a simultaneous erase, charges are removed from charge accumulation layers of the memory cells so that the threshold values of the memory cells are initialized. The threshold initialization is performed on the series-arrayed memory cell transistors in the NAND cell block in sequence.

摘要翻译： 公开了具有NAND单元结构的可擦除可编程只读存储器，其包括NAND单元块，每个NAND单元具有连接到相应位线的选择晶体管和存储单元晶体管的串联阵列。 每个单元晶体管具有浮置栅极和控制栅极。 字线连接到单元晶体管的控制栅极。 在数据擦除模式下，通过向存储单元的控制栅极施加“H”电平电位，并将位线的“L”电平电位同时擦除所有存储单元。 在这种同时擦除之前，从存储器单元的电荷累积层去除电荷，使得存储单元的阈值被初始化。 对NAND单元块中的串联存储单元晶体管依次执行阈值初始化。

公开(公告)号：US5597748A

公开(公告)日：1997-01-28

申请号：US247589

申请日：1994-05-23

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5397723A

公开(公告)日：1995-03-14

申请号：US728585

申请日：1991-07-11

申请人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

发明人： Riichiro Shirota ,  Masaki Momodomi ,  Ryozo Nakayama ,  Seiichi Aritome ,  Ryouhei Kirisawa ,  Tetsuro Endoh ,  Shigeyoshi Watanabe

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265 ,  H01L21/465

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11517

摘要： A process for forming an array of FATMOS transistors serving as memory cells of a NAND cell type EEPROM. A multi-layered structure is provided on a substrate with two stacked conductive layers insulated by an intermediate insulative layer, the first or inner conductive layer being insulated by a first insulative layer from the substrate, the second or outer conductive layer being covered with a second insulative layer. The second insulative layer is etched to define a first array of etched layer portions. A photoresist layer is deposited and etched to define a second array of layer portions, each of which is positioned between two neighboring ones of the first array of layer portions. The multi-layered structure is etched with the first and second layer portions being as a mask, to thereby form an array of a plurality of pairs of insulated gate electrodes above the substrate. A chosen impurity is doped into the substrate with the insulated gate electrodes serving as a mask to thereby form impurity-doped regions in the substrate.

摘要翻译： 用于形成用作NAND单元型EEPROM的存储单元的FATMOS晶体管阵列的工艺。 多层结构设置在具有由中间绝缘层绝缘的两个层叠导电层的基板上，第一或内部导电层由与基板隔开的第一绝缘层，第二或外部导电层被第二 绝缘层。 蚀刻第二绝缘层以限定蚀刻层部分的第一阵列。 沉积和蚀刻光致抗蚀剂层以限定层部分的第二阵列，每个层部分位于层部分的第一阵列中的两个相邻的层部分之间。 用第一和第二层部分作为掩模蚀刻多层结构，从而在衬底上形成多对绝缘栅电极的阵列。 将所选择的杂质掺杂到衬底中，其中绝缘栅电极用作掩模，从而在衬底中形成杂质掺杂区域。

公开(公告)号：US5824583A

公开(公告)日：1998-10-20

申请号：US949819

申请日：1997-10-14

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： 本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。

公开(公告)号：US5323039A

公开(公告)日：1994-06-21

申请号：US499342

申请日：1990-06-21

申请人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

发明人： Masamichi Asano ,  Hiroshi Iwahashi ,  Ryouhei Kirisawa ,  Ryozo Nakayama ,  Satoshi Inoue ,  Riichiro Shirota ,  Tetsuo Endoh ,  Fujio Masuoka

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/68

CPC分类号： H01L27/11519 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.

摘要翻译： PCT No.PCT / JP89 / 00942 Sec。 371 1990年6月21日第 102（e）日期1990年6月21日PCT提交1989年9月14日PCT公布。 公开号WO90 / 04855 日期为1990年5月3日。本发明涉及具有能够电擦除和写入数据的非易失性存储单元的非易失性半导体存储器。 每个存储单元具有形成在沟道区域上方的半导体衬底的表面上的浮置栅极和控制栅极。 浮动栅极部分地覆盖沟道区域。 因此，每个存储单元由浮栅晶体管和增强型晶体管的并联连接构成。 浮栅晶体管在沟道区域的宽度方向中的一个方向上位移，或部分仅覆盖沟道区域的宽度方向的中心部分。 多个存储单元串联连接以构成基本块。 相邻的基本块由增强型MOS晶体管分开。 在该存储器中，使用相同的掩模，以彼此对准的方式形成存储单元（浮置栅极）和增强型MOS晶体管（栅极）。 此外，在该存储器中，使用相同的掩模，以彼此对准的方式形成控制栅极和浮动栅极。