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10 条记录 (耗时 0.021 秒)

    Packet switching system
    1.
    发明授权
    Packet switching system 失效
    分组交换系统

    公开(公告)号：US4827473A

    公开(公告)日：1989-05-02

    申请号：US66766

    申请日：1987-05-29

    申请人： Kazuo Tsuzuki ,  Yoshinori Yoshida ,  Toshio Ishizuka ,  Mitsugu Anezaki

    发明人： Kazuo Tsuzuki ,  Yoshinori Yoshida ,  Toshio Ishizuka ,  Mitsugu Anezaki

    IPC分类号： H04L12/863 ,  H04L12/933 ,  H04L12/937 ,  H04J3/12

    CPC分类号： H04L12/56 ,  H04L49/102 ,  H04L49/254 ,  H04L49/40

    摘要： A packet switching system for achieving high-speed packet switching on data lines having the X.25 protocol of the C.C.I.T.T. It includes a plurality of data line apparatuses (DLC: 10, 11, and 1N), a call connection control information transfer bus commonly connected to the plurality of data line apparatuses (CB: 2), a specialized data transfer bus for data packets (DB: 4), a packet buffer state information transfer bus for transmitting and receiving call state information (SB: 6), and a call connection controlling processor connected to the call connection control information transfer bus (CP: 3). Each of the data line apparatuses has a receive packet storing circuit (DTRQ: 102) provided with a receive packet buffer of the first-in random out (FIRO) memory, and a transmit packet storing circuit (DTSQ: 105) provided with a transmit packet buffer of the FIRO memory.

    摘要翻译： PCT No.PCT / JP86 / 00498 Sec。 371日期1987年5月29日 102（e）日期1987年5月29日PCT提交1986年9月29日PCT公布。 公开号WO87 / 02207 日期：1987年4月9日。一种分组交换系统，用于在具有C.C.I.T.T.T.的X.25协议的数据线上实现高速分组交换。 它包括多个数据线设备（DLC：10,11和1N），一个通用连接到多个数据线设备（CB：2）的呼叫连接控制信息传输总线，用于数据分组的专用数据传输总线 DB：4），用于发送和接收呼叫状态信息（SB：6）的分组缓冲器状态信息传输总线，以及连接到呼叫连接控制信息传输总线（CP：3）的呼叫连接控制处理器。 每个数据线设备具有设置有先进随机输出（FIRO）存储器的接收分组缓冲器的接收分组存储电路（DTRQ：102）和设置有传输的发送分组存储电路（DTSQ：105） FIRO存储器的数据包缓冲区。

    Integrated communications system for HDLC variable-length data packets and fixed-length voice/video packets
    4.
    发明授权
    Integrated communications system for HDLC variable-length data packets and fixed-length voice/video packets 失效
    用于HDLC可变长度数据分组和固定长度语音/视频分组的集成通信系统

    公开(公告)号：US5007045A

    公开(公告)日：1991-04-09

    申请号：US475484

    申请日：1990-02-05

    申请人： Kazuo Tsuzuki

    发明人： Kazuo Tsuzuki

    IPC分类号： H04L29/08 ,  H04J3/24 ,  H04N7/26 ,  H04N7/60 ,  H04N7/62

    CPC分类号： H04N21/434 ,  H04J3/247 ,  H04N19/37 ,  H04N21/236 ,  H04N21/238

    摘要： In an integrated communications system, HDLC variable-length packets and non-HDLC fixed-length packets are decomposed into cells and a cell identifier is generated for each of the cells for identifying its type. A frame sync code is transmitted from one end of a transmission channel, and the cell identifier and each of the cells are assembled into a field and a plurality of such fields are assembled into a frame for transmission. The frame sync code is detected at the other end of the transmission channel as a timing reference and the frame is deassembled into fields in response to the timing reference and each field is deassembled into a cell identifier and a cell. According to each deassembled cell identifier, the cells of each field are composed into the original HDLC variable-length packet of non-HDLC fixed-length packet.

    Thioether derivatives of tylosin
    5.
    发明授权
    Thioether derivatives of tylosin 失效
    泰乐菌素的硫醚衍生物

    公开(公告)号：US4594338A

    公开(公告)日：1986-06-10

    申请号：US702533

    申请日：1985-02-19

    申请人： Satoshi Omura ,  Kazuo Tsuzuki

    发明人： Satoshi Omura ,  Kazuo Tsuzuki

    IPC分类号： A61K31/70 ,  A61K31/7042 ,  A61K31/7048 ,  A61P31/04 ,  C07H17/08

    CPC分类号： C07H17/08

    摘要： 11-Thioether and certain C-20 acetal and thioacetal derivatives of tylosin and demycarosyltylosin are effective antibacterial agents. Processes for preparing, formulations containing, and methods of treating bacterial infections with these derivatives are provided.

    摘要翻译： 十一硫醚和泰乐菌素和demycarosyltylosin的某些C-20缩醛和硫代缩醛衍生物是有效的抗菌剂。 提供了制备方法，含有制剂，以及用这些衍生物治疗细菌感染的方法。

    Method and apparatus for generating planarizing pattern and semiconductor integrated circuit device
    6.
    发明授权
    Method and apparatus for generating planarizing pattern and semiconductor integrated circuit device 失效
    用于产生平面图案和半导体集成电路器件的方法和装置

    公开(公告)号：US5970238A

    公开(公告)日：1999-10-19

    申请号：US816536

    申请日：1997-03-13

    申请人： Hidenori Shibata ,  Kazuo Tsuzuki

    发明人： Hidenori Shibata ,  Kazuo Tsuzuki

    IPC分类号： G06F17/50 ,  H01L23/528

    CPC分类号： G06F17/5077 ,  H01L23/528 ,  H01L2924/0002

    摘要： A dummy pattern is generated by enlarging a wiring pattern by a specified amount to generate an enlarged wiring pattern and deleting the overlapping portion of a first dummy original pattern composed of a group of squares with the enlarged wiring pattern. The dummy pattern is reduced by the specified amount to generate a reduced dummy pattern, which is enlarged by the specified amount to generate a planarizing pattern. The planarizing pattern is combined with the wiring pattern to generate a final pattern.

    摘要翻译： 通过将布线图案放大规定量来生成伪图案，生成放大布线图案，并且删除由具有放大布线图案的正方形组构成的第一虚拟原稿图案的重叠部分。 虚拟图案减少指定的量以产生减小的伪图案，其被放大指定的量以产生平坦化图案。 平面图与布线图案组合以产生最终图案。

    Method for designing layout of semiconductor device, storage medium having stored thereon program for executing the layout designing method, and semiconductor device
    7.
    发明授权
    Method for designing layout of semiconductor device, storage medium having stored thereon program for executing the layout designing method, and semiconductor device 有权
    用于设计半导体器件布局的方法，其上存储有用于执行布局设计方法的程序的存储介质和半导体器件

    公开(公告)号：US06532581B1

    公开(公告)日：2003-03-11

    申请号：US09345485

    申请日：1999-07-01

    申请人： Masahiko Toyonaga ,  Kazuo Tsuzuki

    发明人： Masahiko Toyonaga ,  Kazuo Tsuzuki

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068

    摘要： A method for designing a layout of a semiconductor device includes the steps of: a) preparing a first layout corresponding to a first netlist and including a component layout and a number n of, or first to nth (where n≧2), interconnection planar layouts to be sequentially stacked on the component layout; b) receiving a second netlist, which is different from the first netlist; c) selecting at least one of the interconnection planar layouts from the first layout, the number of the interconnection planar layouts selected being equal to or smaller than n−1; and d) producing a second layout, corresponding to the second netlist, by changing the physical arrangement of the at least one interconnection planar layout selected, the second layout including the component layout, the at least one interconnection planar layout with the changed arrangement, and the other interconnection planar layouts that have not been selected from the first layout.

    摘要翻译： 一种用于设计半导体器件的布局的方法包括以下步骤：a）准备与第一网表对应的第一布局，并且包括元件布局，n或n至第n（n = 2），互连 平面布局顺序堆叠在组件布局上; b）接收与第一网表不同的第二网表; c）从所述第一布局中选择所述互连平面布局中的至少一个，所选择的互连平面布局的数量等于或小于n-1; 以及d）通过改变所选择的所述至少一个互连平面布局的物理排列，包括组件布局的第二布局，具有改变的布置的至少一个互连平面布局，产生与第二网表对应的第二布局，以及 尚未从第一布局中选择的其他互连平面布局。

    Semiconductor integrated logic circuit device
    9.
    发明授权
    Semiconductor integrated logic circuit device 失效
    半导体集成逻辑电路器件

    公开(公告)号：US5986292A

    公开(公告)日：1999-11-16

    申请号：US997944

    申请日：1997-12-24

    申请人： Hiroshi Mizuno ,  Youichirou Mae ,  Hidenori Shibata ,  Kazuo Tsuzuki

    发明人： Hiroshi Mizuno ,  Youichirou Mae ,  Hidenori Shibata ,  Kazuo Tsuzuki

    IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L27/10

    CPC分类号： H01L27/092 ,  H01L27/0207

    摘要： An inverter-type basic cell, with a hexagonal contour, comprises one CMOS device pair arrangement including an n-channel transistor and a p-channel transistor. The inverter-type basic cell has a gate region annularly formed and connected in parallel with the n-channel and p-channel transistors, a sectoral drain diffusion region having a vertex at the center of the annularly-formed gate region, and a source diffusion region that is formed outside of the gate region in such a way as to define a shape having two opposing sides that lie on the prolongation of the two radii of the sectoral drain diffusion region.

    摘要翻译： 具有六边形轮廓的逆变器型基本单元包括包括n沟道晶体管和p沟道晶体管的一个CMOS器件对布置。 逆变器型基电池具有环形地形成并与n沟道和p沟道晶体管并联连接的栅极区域，在环状形成的栅极区域的中心具有顶点的扇形漏极扩散区域和源极扩散区域 区域，其形成在栅极区域外部，以限定具有位于扇形漏极扩散区域的两个半径的延伸的两个相对侧面的形状。