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公开(公告)号：US06338994B1
公开(公告)日：2002-01-15
申请号：US09475033
申请日：1999-12-30
申请人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
发明人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
IPC分类号： H01L218242
CPC分类号： H01L28/55 , H01L27/10852
摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.
摘要翻译： 一种形成在半导体衬底上的具有底电极，铁电体膜和顶电极的半导体器件，其中，强电介质膜的每个主横截面相对于半导体衬底的主表面的角度小于75 度。 如果用单一光刻工艺步骤蚀刻上电极，铁电体膜和底电极，则将铁电膜形成具有这种角度的横截面中的梯形，提供了在顶电极和底电极之间没有电短路的微电容器。 该新技术实现了适用于高度集成的存储器件的微观存储单元结构。
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公开(公告)号：US06432767B1
公开(公告)日：2002-08-13
申请号：US09897615
申请日：2001-07-03
申请人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
发明人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
IPC分类号： H01L218242
摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.
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公开(公告)号：US6097051A
公开(公告)日：2000-08-01
申请号：US755602
申请日：1996-11-25
申请人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
发明人： Kazuyoshi Torii , Hiroshi Kawakami , Hiroshi Miki , Keiko Kushida , Yoshihisa Fujisaki , Masahiro Moniwa
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： H01L28/55 , H01L27/10852
摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.
摘要翻译： 一种形成在半导体衬底上的具有底电极，铁电体膜和顶电极的半导体器件，其中，强电介质膜的每个主横截面相对于半导体衬底的主表面的角度小于75 度。 如果用单一光刻工艺步骤蚀刻上电极，铁电体膜和底电极，则将铁电膜形成具有这种角度的横截面中的梯形，提供了在顶电极和底电极之间没有电短路的微电容器。 该新技术实现了适用于高度集成的存储器件的微观存储单元结构。
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公开(公告)号：US06800889B2
公开(公告)日：2004-10-05
申请号：US10073240
申请日：2002-02-13
IPC分类号： H01L2976
摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。
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公开(公告)号：US06462368B2
公开(公告)日：2002-10-08
申请号：US10059256
申请日：2002-01-31
IPC分类号： H01L2976
CPC分类号： H01L27/10855 , H01L21/76885 , H01L27/10894 , H01L28/91
摘要： A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layer of a switching transistor is self-aligned. As a result, side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.
摘要翻译： 在下电极的底表面和将下电极连接到开关晶体管的扩散层之一的互连之间延伸的扩散防止层是自对准的。 结果，由于通过使用虚拟膜形成孔图案，所以制造侧沟槽，并且即使存储部分的接触插塞与扩散防止层不对准，接触插塞也不与电介质膜直接接触 具有很高的介电常数。 因此，可以获得高度可靠的装置。
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公开(公告)号：US06396092B1
公开(公告)日：2002-05-28
申请号：US09381396
申请日：1999-09-20
IPC分类号： H01L2906
摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。
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公开(公告)号：US06380574B1
公开(公告)日：2002-04-30
申请号：US09674392
申请日：2000-10-31
IPC分类号： H01L2976
CPC分类号： H01L21/7687 , H01L27/10814 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10894 , H01L28/75
摘要： A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.
摘要翻译： 在下电极的底表面和将下电极连接到开关晶体管的一个扩散层的布线之间延伸的扩散防止层是自对准的。 结果，由于通过使用虚拟膜形成孔图案，所以不产生侧沟槽，并且即使存储部分的接触插塞与扩散防止层不对准，接触插塞不与电介质直接接触 具有高介电常数的薄膜。 因此，可以获得高度可靠的装置。
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公开(公告)号：US6144052A
公开(公告)日：2000-11-07
申请号：US142011
申请日：1998-08-31
申请人： Keiko Kushida , Masahiko Hiratani , Kazuyoshi Torii , Shinichiro Takatani , Hiroshi Miki , Yuuichi Matsui , Yoshihisa Fujisaki
发明人： Keiko Kushida , Masahiko Hiratani , Kazuyoshi Torii , Shinichiro Takatani , Hiroshi Miki , Yuuichi Matsui , Yoshihisa Fujisaki
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/72
CPC分类号： H01L27/10852 , H01L28/55 , H01L28/60 , H01L27/10814 , H01L27/10888
摘要： An oriented polycrystal silicon film or an amorphous silicon film 52 is disposed on the whole area beneath a conductive diffusion barrier 61 under a lower electrode of a ferroelectric capacitor. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.
摘要翻译： PCT No.PCT / JP96 / 00579 Sec。 371日期1998年8月31日 102（e）1998年8月31日PCT 1996年3月8日PCT公布。 公开号WO97 / 33316 PCT 日期1997年9月12日在铁电电容器的下电极下方的导电性扩散阻挡层61的下方的整个区域上设置取向多晶硅膜或非晶硅膜52。 结果，导电扩散阻挡层，下电极和电容器铁电体膜成为取向膜; 因此，即使在微小的半导体器件中也可以减小电容器的信号变化，并获得高可靠性的半导体器件。
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9.发明申请公开(公告)号：US20050051821A1
公开(公告)日：2005-03-10
申请号：US10920344
申请日：2004-08-18
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
摘要翻译： 电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。 在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。 因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。 另外，可以提高装置的长期可靠性。
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10.发明授权公开(公告)号：US07256437B2
公开(公告)日：2007-08-14
申请号：US10920344
申请日：2004-08-18
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： H01L29/76
摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
摘要翻译： 电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。 在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。 因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。 另外，可以提高装置的长期可靠性。
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