公开(公告)号：US06338994B1

公开(公告)日：2002-01-15

申请号：US09475033

申请日：1999-12-30

申请人： Kazuyoshi Torii ,  Hiroshi Kawakami ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Masahiro Moniwa

发明人： Kazuyoshi Torii ,  Hiroshi Kawakami ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Masahiro Moniwa

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L27/10852

摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.

摘要翻译： 一种形成在半导体衬底上的具有底电极，铁电体膜和顶电极的半导体器件，其中，强电介质膜的每个主横截面相对于半导体衬底的主表面的角度小于75 度。 如果用单一光刻工艺步骤蚀刻上电极，铁电体膜和底电极，则将铁电膜形成具有这种角度的横截面中的梯形，提供了在顶电极和底电极之间没有电短路的微电容器。 该新技术实现了适用于高度集成的存储器件的微观存储单元结构。

公开(公告)号：US06432767B1

公开(公告)日：2002-08-13

申请号：US09897615

申请日：2001-07-03

申请人： Kazuyoshi Torii ,  Hiroshi Kawakami ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Masahiro Moniwa

发明人： Kazuyoshi Torii ,  Hiroshi Kawakami ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Masahiro Moniwa

IPC分类号： H01L218242

摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.

公开(公告)号：US6097051A

公开(公告)日：2000-08-01

申请号：US755602

申请日：1996-11-25

申请人： Kazuyoshi Torii ,  Hiroshi Kawakami ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Masahiro Moniwa

发明人： Kazuyoshi Torii ,  Hiroshi Kawakami ,  Hiroshi Miki ,  Keiko Kushida ,  Yoshihisa Fujisaki ,  Masahiro Moniwa

IPC分类号： H01L21/8247 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L28/55 ,  H01L27/10852

摘要： A semiconductor device having a bottom electrode, a ferroelectric film, and a top electrode formed on a semiconductor substrate, wherein the angle of each of the main cross sectional sides of the ferroelectric film relative to the main surface of the semiconductor substrate is less than 75 degrees. Forming the ferroelectric film into the trapezoid in cross section having such an angle provides a microscopic capacitor without electrical short-circuit between the top and bottom electrodes if the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step. The novel technique implements a microscopic memory cell structure suitable for highly integrated memory devices.

摘要翻译： 一种形成在半导体衬底上的具有底电极，铁电体膜和顶电极的半导体器件，其中，强电介质膜的每个主横截面相对于半导体衬底的主表面的角度小于75 度。 如果用单一光刻工艺步骤蚀刻上电极，铁电体膜和底电极，则将铁电膜形成具有这种角度的横截面中的梯形，提供了在顶电极和底电极之间没有电短路的微电容器。 该新技术实现了适用于高度集成的存储器件的微观存储单元结构。

公开(公告)号：US07701020B2

公开(公告)日：2010-04-20

申请号：US12364279

申请日：2009-02-02

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L27/088

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US07598133B2

公开(公告)日：2009-10-06

申请号：US11714865

申请日：2007-03-07

申请人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

发明人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/331 ,  H01L21/76

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104

摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。 垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的叠层，形成在层叠体的侧壁表面上的氧化硅栅绝缘膜和形成的栅电极 以覆盖层压板的侧壁。 垂直MISFET是完全耗尽型MISFET。

公开(公告)号：US20090140342A1

公开(公告)日：2009-06-04

申请号：US12364279

申请日：2009-02-02

申请人： Hiraku CHAKIHARA ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku CHAKIHARA ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L29/78

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US07495289B2

公开(公告)日：2009-02-24

申请号：US11418024

申请日：2006-05-05

申请人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

发明人： Hiraku Chakihara ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Makoto Mizuno ,  Keiji Okamoto ,  Mitsuhiro Noguchi ,  Tadanori Yoshida ,  Yasuhiko Takahshi ,  Akio Nishida

IPC分类号： H01L29/78 ,  G11C11/412

CPC分类号： H01L29/6675 ,  H01L21/823885 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7833 ,  H01L29/78642

摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.

摘要翻译： 垂直MISFET形成在驱动MISFET和传输MISFET上。 垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极 插入其间。 在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。 下半导体层，中间半导体层和上半导体层均由硅膜构成。 下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

公开(公告)号：US20070173006A1

公开(公告)日：2007-07-26

申请号：US11714865

申请日：2007-03-07

申请人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

发明人： Masahiro Moniwa ,  Hiraku Chakihara ,  Kousuke Okuyama ,  Yasuhiko Takahashi

IPC分类号： H01L21/8234

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L27/1104

摘要： A memory cell of an SRAM has two drive MISFETs and two vertical MISFETs. The p channel vertical MISFETs are formed above the n channel drive MISFETs. The vertical MISFETs respectively mainly comprise laminate formed of a lower semiconductor layer, intermediate semiconductor layer and upper semiconductor layer laminated in this sequence, a gate insulating film of silicon oxide formed on the surface of the side wall of the laminate, and a gate electrode formed so as to cover the side wall of the laminate. The vertical MISFETs are perfect depletion type MISFETs.

摘要翻译： SRAM的存储单元具有两个驱动MISFET和两个垂直MISFET。 p沟道垂直MISFET形成在n沟道驱动MISFET的上方。 垂直MISFET分别主要包括由下半导体层，中间半导体层和按此顺序层叠的上半导体层形成的叠层，形成在层叠体的侧壁表面上的氧化硅栅绝缘膜和形成的栅电极 以覆盖层压板的侧壁。 垂直MISFET是完全耗尽型MISFET。

公开(公告)号：US07187039B2

公开(公告)日：2007-03-06

申请号：US11101446

申请日：2005-04-08

申请人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

发明人： Yasushi Koubuchi ,  Koichi Nagasawa ,  Masahiro Moniwa ,  Youhei Yamada ,  Toshifumi Takeda

IPC分类号： H01L29/76

CPC分类号： H01L23/562 ,  G03F9/7076 ,  G03F9/7084 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/585 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

公开(公告)号：US20060035434A1

公开(公告)日：2006-02-16

申请号：US10493443

申请日：2002-10-10

申请人： Tsuyoshi Tabata ,  Kazuo Nakazato ,  Hiroshi Kujirai ,  Masahiro Moniwa ,  Hideyuki Matsuoka ,  Teruaki Kisu ,  Teruo Kisu ,  Haruko Kisu ,  Satoru Haga

发明人： Tsuyoshi Tabata ,  Kazuo Nakazato ,  Hiroshi Kujirai ,  Masahiro Moniwa ,  Hideyuki Matsuoka ,  Teruaki Kisu ,  Teruo Kisu ,  Haruko Kisu ,  Satoru Haga

IPC分类号： H01L21/336

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/10876 ,  Y10S257/903

摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).

摘要翻译： 半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。 在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼 来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。