公开(公告)号：US06767777B2

公开(公告)日：2004-07-27

申请号：US10068014

申请日：2002-02-05

申请人： Keith A. Joyner ,  Mark S. Rodder

发明人： Keith A. Joyner ,  Mark S. Rodder

IPC分类号： H01L21338

CPC分类号： H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

摘要翻译： 一种制造晶体管的方法，包括：提供具有第一表面的半导体层，设置在第一表面上的电介质层，设置在电介质层上的栅电极，与栅电极的至少一部分相邻的绝缘层的晶体管组件， 以及邻近绝缘层的至少一部分的氮化物间隔层。 该方法还包括在第一表面的一部分上沉积将与半导体层反应以形成硅化物并除去未反应材料的材料。 该方法还包括蚀刻氮化物间隔层，沉积与氮化物间隔层的至少一部分相邻的预金属间隔层和至少部分第一表面，蚀刻去除前金属间隔层的一部分以暴露部分 第一表面的硅化部分，并与第一表面的硅化部分形成接触。

公开(公告)号：US07459734B2

公开(公告)日：2008-12-02

申请号：US10846741

申请日：2004-05-14

申请人： Keith A. Joyner ,  Mark S. Rodder

发明人： Keith A. Joyner ,  Mark S. Rodder

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76897 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a transistor includes providing a transistor assembly having a semiconductor layer with a first surface, a dielectric layer disposed on the first surface, a gate electrode disposed on the dielectric layer, an insulation layer adjacent at least part of the gate electrode, and a nitride spacer layer adjacent at least part of the insulation layer. The method also includes depositing, on part of the first surface, a material that will react with the semiconductor layer to form silicide and removing the unreacted material. The method further includes etching the nitride spacer layer, depositing a pre-metal spacer layer adjacent at least part of the nitride spacer layer and at least part of the first surface, etch removing a portion of the pre-metal spacer layer to expose part of the silicided portion of the first surface, and forming a contact with the silicided portion of the first surface.

摘要翻译： 一种制造晶体管的方法，包括：提供具有第一表面的半导体层，设置在第一表面上的电介质层，设置在电介质层上的栅电极，与栅电极的至少一部分相邻的绝缘层的晶体管组件， 以及邻近绝缘层的至少一部分的氮化物间隔层。 该方法还包括在第一表面的一部分上沉积将与半导体层反应以形成硅化物并除去未反应材料的材料。 该方法还包括蚀刻氮化物间隔层，沉积与氮化物间隔层的至少一部分相邻的预金属间隔层和至少部分第一表面，蚀刻去除前金属间隔层的一部分以暴露部分 第一表面的硅化部分，并与第一表面的硅化部分形成接触。

公开(公告)号：US06376285B1

公开(公告)日：2002-04-23

申请号：US09314983

申请日：1999-05-20

申请人： Keith A. Joyner ,  Leland S. Swanson

发明人： Keith A. Joyner ,  Leland S. Swanson

IPC分类号： H01L2100

CPC分类号： H01L21/7627 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3167

摘要： An epitaxial layer of silicon is grown on a layer of partially-oxidized porous silicon, then covered by a capping layer which provides structural support and prevents oxidation of the epitaxial layer. A high-temperature anneal allows the partially oxidized silicon layer to separate into distinct layers of silicon and SiO2, producing a buried oxide layer. This method provides a low cost means of producing silicon-on-insulator (SOI) wafers.

摘要翻译： 硅的外延层在部分氧化的多孔硅层上生长，然后被覆盖层覆盖，该覆盖层提供结构支撑并防止外延层的氧化。 高温退火使得部分氧化的硅层分离成不同的硅层和SiO 2层，产生掩埋氧化物层。 该方法提供了制造绝缘体上硅（SOI）晶片的低成本手段。

公开(公告)号：US5440132A

公开(公告)日：1995-08-08

申请号：US220308

申请日：1994-03-30

申请人： Keith A. Joyner ,  James B. Hollingsworth

发明人： Keith A. Joyner ,  James B. Hollingsworth

IPC分类号： H01L21/683 ,  H01L21/265 ,  H01L21/687 ,  H01J37/317

CPC分类号： H01L21/68764 ,  H01L21/68771 ,  H01L21/68792 ,  H01J2237/2001 ,  H01J2237/31701

摘要： An implantation system (10) is provided that comprises a rotating drum (12) which holds a wafer chuck (28) which in turn holds a semiconductor wafer (26). The wafer chuck (28) rotates during the implantation of oxygen from an oxygen beam (24) created by a beam generator (22). The wafer chuck (28) is rotated via shaft (30) from a motor (32). The wafer chuck (28) also holds a thermal reflector (36) which allows for control of the temperature of the wafer during the implantation process.

摘要翻译： 提供一种植入系统（10），其包括保持晶片卡盘（28）的旋转滚筒（12），所述晶片卡盘（28）又保持半导体晶片（26）。 在从由光束发生器（22）产生的氧气束（24）注入氧气期间，晶片卡盘（28）旋转。 晶片卡盘（28）经由轴（30）从马达（32）旋转。 晶片卡盘（28）还保持热反射器（36），其允许在植入过程期间控制晶片的温度。

公开(公告)号：US5429955A

公开(公告)日：1995-07-04

申请号：US966236

申请日：1992-10-26

申请人： Keith A. Joyner ,  Mohamed K. El-Ghor ,  Harold H. Hosack

发明人： Keith A. Joyner ,  Mohamed K. El-Ghor ,  Harold H. Hosack

IPC分类号： H01L21/02 ,  H01L21/265 ,  H01L21/76 ,  H01L21/762 ,  H01L27/00 ,  H01L27/12

CPC分类号： H01L21/76243 ,  H01L21/26533

摘要： A method for constructing a semiconductor-on-insulator is provided. A sacrificial layer (12) of a predetermined thickness is first formed on a semiconductor wafer (10) surface. The wafer (10) is then subjected to an ion implantation process to place the ions (16) at predetermined depths below the semiconductor wafer surface. During the implantation process, the sacrificial layer (12) is gradually sputtered away and thereby compensating the gradual outgrowth of the silicon surface due to the volume of the implanted ions (16). A post-implant anneal is performed to allow the ions (16) to react with the semiconductor to form a buried insulating layer (24).

摘要翻译： 提供一种用于构造绝缘体上半导体的方法。 首先在半导体晶片（10）表面上形成预定厚度的牺牲层（12）。 然后对晶片（10）进行离子注入工艺，以将离子（16）放置在半导体晶片表面下方的预定深度处。 在注入过程中，牺牲层（12）被逐渐地溅射掉，从而由于注入的离子（16）的体积补偿了硅表面的逐渐向外生长。 进行植入后退火以允许离子（16）与半导体反应以形成掩埋绝缘层（24）。

公开(公告)号：US5364800A

公开(公告)日：1994-11-15

申请号：US82080

申请日：1993-06-24

申请人： Keith A. Joyner

发明人： Keith A. Joyner

IPC分类号： H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L21/76243 ,  Y10S438/981

摘要： A preferred embodiment of this invention is a silicon-on-insulator structure comprising a semiconductor substrate (e.g. Si 36), a buried insulator layer (e.g. SiO.sub.2 34) overlaying the substrate, wherein the buried layer is buried at two or more predetermined depths, and a surface silicon layer (e.g. Si 32) overlaying the buried insulator, wherein the surface silicon layer has two or more predetermined thicknesses. Generally, by patterning and etching a screening material (e.g. SiO.sub.2 30) prior to ion implantation, preselected areas of the substrate with less or no screen material are formed with a thicker surface silicon layer, while other areas with more screen material are formed with a thinner surface silicon layer. The areas of different surface silicon thickness can be used to implement devices with different characteristics based on those thicknesses, within the same integrated circuit. Generally, relatively thinner regions can be used for faster speed devices and relatively thicker regions can be used for greater current carrying capability. The novel technique of depositing, patterning and etching a layer of screening material before implantation can also be used to create a substrate with both bulk and SOI substrate regions, with different portions of a circuit built in each region. Generally, such a substrate can be used to create integrated circuits that have high voltage isolation between different blocks of the circuit. The SOI/bulk substrate can also be used to fabricate integrated circuits which contain low voltage logic and which also regulate large amounts of current at high voltage.

摘要翻译： 本发明的优选实施例是包括半导体衬底（例如Si 36），覆盖衬底的掩埋绝缘体层（例如SiO 2 34）的绝缘体上硅结构，其中掩埋层被埋在两个或更多个预定深度处， 以及覆盖所述埋入绝缘体的表面硅层（例如Si 32），其中所述表面硅层具有两个或更多个预定厚度。 通常，通过在离子注入之前图案化和蚀刻掩模材料（例如SiO 2 30），具有更少或不具有筛网材料的基板的预选区域形成有更厚的表面硅层，而具有更多屏蔽材料的其它区域形成有 较薄的表面硅层。 不同表面硅厚度的区域可以用于在相同的集成电路内实现基于这些厚度的不同特性的器件。 通常，相对较薄的区域可用于更快的速度装置，并且相对较厚的区域可用于更大的载流能力。 在植入之前沉积，图案化和蚀刻一层筛选材料的新技术也可以用于产生具有大块和SOI衬底区域的衬底，其中每个区域内部的电路的不同部分。 通常，这样的衬底可用于产生在电路的不同块之间具有高电压隔离的集成电路。 SOI /体基板也可用于制造含有低电压逻辑的集成电路，并且还可以在高电压下调节大量的电流。

公开(公告)号：US06214699B1

公开(公告)日：2001-04-10

申请号：US09281544

申请日：1999-03-30

申请人： Keith A. Joyner

发明人： Keith A. Joyner

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： In order to form an isolation structure in a substrate, a blocking layer (13, 14) is fabricated over the substrate (12), after which portions of the blocking layer and the substrate are removed at an isolation region (22). A dielectric layer (26) is then deposited over the blocking layer and the isolation region. Thereafter, a chemical-mechanical polishing process is carried out on the dielectric layer, so as to remove a substantial portion of the dielectric layer disposed above an upper surface of the blocking layer. A non-patterned etch is then carried out on the dielectric layer, in order to remove a remaining portion of the dielectric layer disposed above the upper surface of the blocking layer.

摘要翻译： 为了在衬底中形成隔离结构，在衬底（12）上制造阻挡层（13,14），然后在隔离区域（22）处去除阻挡层和衬底的部分。 然后将介电层（26）沉积在阻挡层和隔离区上。 此后，在电介质层上进行化学机械抛光工艺，以去除设置在阻挡层上表面上方的电介质层的大部分。 然后在电介质层上进行非图案化蚀刻，以便去除设置在阻挡层的上表面上方的电介质层的剩余部分。

公开(公告)号：US06171969B2

公开(公告)日：2001-01-09

申请号：US09266520

申请日：1999-03-11

申请人： Keith A. Joyner

发明人： Keith A. Joyner

IPC分类号： H01L21311

CPC分类号： H01L21/26513 ,  H01L21/30604

摘要： A semiconductor device and method having mesas with uniformly-doped regions 18. A semiconductor substrate 10 is uniformly-doped and then, mesas 12 are formed in the semiconductor surface. Advantages of the invention include a mesa 12 having a uniformly-doped surface, solving the problem of non-uniformity of doping density caused by lateral ion straggling found in the prior art. Another advantage of the invention is a structure having evenly-doped mesas yet undoped trenches.

摘要翻译： 具有均匀掺杂区域18的台面的半导体器件和方法。半导体衬底10被均匀掺杂，然后在半导体表面中形成台面12。 本发明的优点包括具有均匀掺杂表面的台面12，解决了现有技术中发现的由横向离子交错引起的掺杂密度不均匀的问题。 本发明的另一个优点是具有均匀掺杂的台面但未掺杂的沟槽的结构。

公开(公告)号：US6118161A

公开(公告)日：2000-09-12

申请号：US69569

申请日：1998-04-29

申请人： Richard A. Chapman ,  Theodore W. Houston ,  Keith A. Joyner

发明人： Richard A. Chapman ,  Theodore W. Houston ,  Keith A. Joyner

IPC分类号： H01L21/335 ,  H01L21/336 ,  H01L29/04 ,  H01L29/786 ,  H01L29/78

CPC分类号： H01L29/785 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

摘要： A transistor (100) having a strip channel or channels (108) in which the current flow in is the lateral direction between source (110) and drain (112). The gate (116) is located on the sidewalls and, if desired, the top of the strip channel (108). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (110) and drain (112) regions to be self-aligned to the gate (116).

摘要翻译： 具有带通道或通道（108）的晶体管（100），其中电流流入其中源极（110）和漏极（112）之间的横向方向。 门（116）位于侧壁上，并且如果需要，位于条形通道（108）的顶部。 在本发明的优选实施例中，使用允许源极（110）和漏极（112）区域与栅极（116）自对准的一次性栅极工艺。

公开(公告)号：US5909628A

公开(公告)日：1999-06-01

申请号：US804484

申请日：1997-02-21

申请人： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

发明人： Amitava Chatterjee ,  Theodore W. Houston ,  Ih-Chin Chen ,  Agerico L. Esquirel ,  Somnath Nag ,  Iqbal Ali ,  Keith A. Joyner ,  Yin Hu ,  Jeffrey Alan McKee ,  Peter Stewart McAnally

IPC分类号： H01L21/76 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/762 ,  H01L29/78

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

摘要翻译： 制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。 在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。 虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。 支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。