公开(公告)号：US08771406B1

公开(公告)日：2014-07-08

申请号：US13772652

申请日：2013-02-21

申请人： Ken Elliott ,  Sonya Elliott

发明人： Ken Elliott ,  Sonya Elliott

IPC分类号： B01D53/02

CPC分类号： B65D90/30 ,  B01D53/0446 ,  B01D53/48 ,  B01D2253/102 ,  B01D2253/1124 ,  B01D2255/20738 ,  B01D2257/304 ,  B01D2257/306 ,  B01D2259/4566 ,  B60P3/2255 ,  B65D90/0066 ,  B65D90/34

摘要： A transport tank with high capacity gas scrubbing includes a vertically extending interior wall horizontally dividing the transport tank into a gas scrubbing chamber and a fluid storage chamber. A floor grate is supported within the gas scrubbing chamber at vertically spaced distance from a bottom of the transport tank and defines a gas distribution space between the floor grate and the tank bottom. A gas distribution pipe is disposed within and longitudinally extends the gas distribution space. A gas inlet is fluidically connected to the gas distribution pipe and passes through an exterior wall of the transport tank. A gas scrubbing is material disposed within the gas scrubbing chamber above the floor grate. And a gas outlet is fluidically connected to the gas scrubbing chamber for venting scrubbed gases.

摘要翻译： 具有高容量气体洗涤的运输罐包括垂直延伸的内壁，其将输送罐水平分割成气体洗涤室和流体储存室。 地板格栅在气体洗涤室内被支撑在与运输罐的底部垂直间隔的距离处，并且限定了地板格栅和罐底之间的气体分配空间。 气体分配管设置在气体分配空间内并纵向延伸。 气体入口与气体分配管流体连接，并通过运输罐的外壁。 气体洗涤是布置在地板格栅上方的气体洗涤室内的材料。 气体出口流体连接到气体洗涤室，用于排出洗涤气体。

公开(公告)号：US07514708B2

公开(公告)日：2009-04-07

申请号：US10420346

申请日：2003-04-22

申请人： Stephen Thomas, III ,  Ken Elliott ,  David H. Chow

发明人： Stephen Thomas, III ,  Ken Elliott ,  David H. Chow

IPC分类号： H01L29/06

CPC分类号： B82Y10/00 ,  H01L29/66151 ,  H01L29/882 ,  Y10S977/712 ,  Y10S977/888

摘要： A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substrate 100 that serves as a foundation for bottom contact layers 102 and a polyimide 700 coating. An ohmic metal contact 300 and emitter metal contact 400 protrude above the polyimide 700 coating exposing the ohmic metal contact 300 and emitter metal contact 400. The contacts are capped with an etch-resistant coating 710 thus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.

摘要翻译： 约80纳米直径的亚微米，具有约5.1比1的峰谷比的共振隧道二极管及其制造方法。 本发明是独特的，因为其性能特性在相当大的谐振隧道二极管中是无法比拟的。 此外，聚酰亚胺钝化和平面化方法在制造谐振隧道二极管方面提供了意想不到的处理优点。 本发明包括用作底部接触层102和聚酰亚胺700涂层的基础的基底100。 欧姆金属触点300和发射极金属触点400突出在暴露欧姆金属触点300和发射极金属触点400的聚酰亚胺700涂层之上。触点被抗蚀涂层710覆盖，从而允许聚酰亚胺蚀刻和其它蚀刻工艺 而不会不利地影响触点。

公开(公告)号：US08242538B1

公开(公告)日：2012-08-14

申请号：US13105668

申请日：2011-05-11

申请人： Peter Deelman ,  Ken Elliott ,  David Chow

发明人： Peter Deelman ,  Ken Elliott ,  David Chow

IPC分类号： H01L31/102

CPC分类号： H01L21/02395 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02631

摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

摘要翻译： 正在公开半导体器件和方法。 半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与 彼此由一个III-V组单独的三层组成。 该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

公开(公告)号：US08193611B1

公开(公告)日：2012-06-05

申请号：US11641917

申请日：2006-12-19

申请人： Rajesh Rajavel ,  Ken Elliott ,  David Chow

发明人： Rajesh Rajavel ,  Ken Elliott ,  David Chow

IPC分类号： H01L29/22

CPC分类号： H01L29/201 ,  H01L29/66462 ,  H01L29/7783

摘要： Material layer structures that have high mobility, a high conduction band barrier and materials that can be implanted to enable higher performance FET device. The structures contain a quantum well layer disposed between two barriers and disposed above a buffer layer and a substrate.

摘要翻译： 具有高迁移率，高导带势垒的材料层结构和可植入的材料以实现更高性能的FET器件。 这些结构包含设置在两个阻挡层之间并设置在缓冲层和基底之上的量子阱层。

公开(公告)号：US07968435B1

公开(公告)日：2011-06-28

申请号：US12491004

申请日：2009-06-24

申请人： Peter Deelman ,  Ken Elliott ,  David Chow

发明人： Peter Deelman ,  Ken Elliott ,  David Chow

IPC分类号： H01L21/20

CPC分类号： H01L21/02395 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02631

摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

摘要翻译： 正在公开半导体器件和方法。 半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与 彼此由一个III-V组单独的三层组成。 该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

公开(公告)号：US07667515B1

公开(公告)日：2010-02-23

申请号：US12156266

申请日：2008-05-31

申请人： Ken Elliott ,  Susan Morton ,  Mark Rodwell

发明人： Ken Elliott ,  Susan Morton ,  Mark Rodwell

IPC分类号： H03H11/26

CPC分类号： H03K17/603 ,  H03K5/131 ,  H03K17/6264 ,  H03K2005/00065 ,  H03K2005/00176

摘要： Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.

摘要翻译： 公开了一种时间延迟发生器200的装置和方法。 该装置包括时间延迟门212，混合器216（吉尔伯特单元电路）和当前数模转换器206.由第一和第二晶体管差分对218和220组成的混频器216接收模拟输入信号202 没有延迟，以及由时间门延迟产生的延迟输入信号210。 数模转换器调节第一控制信号232和第二控制信号238之间的相对电流，有效地改变未延迟的输入信号208和延迟输入信号210的混合，以产生具有时间的延迟的输出信号214，或者 相位延迟基本上等于由数字信号输入204表示的时间延迟。时间延迟发生器表现出降低的相位噪声和线性时间延迟响应。

公开(公告)号：US07598158B1

公开(公告)日：2009-10-06

申请号：US11447338

申请日：2006-06-05

申请人： Peter Deelman ,  Ken Elliott ,  David Chow

发明人： Peter Deelman ,  Ken Elliott ,  David Chow

IPC分类号： H01L21/20

CPC分类号： H01L21/02395 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02631

摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

摘要翻译： 正在公开半导体器件和方法。 半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与 彼此由一个III-V组单独的三层组成。 该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

公开(公告)号：US07446584B2

公开(公告)日：2008-11-04

申请号：US10256099

申请日：2002-09-25

申请人： Ken Elliott ,  Susan Morton ,  Mark Rodwell

发明人： Ken Elliott ,  Susan Morton ,  Mark Rodwell

IPC分类号： H03H11/26

CPC分类号： H03K17/603 ,  H03K5/131 ,  H03K17/6264 ,  H03K2005/00065 ,  H03K2005/00176

摘要： Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.

摘要翻译： 公开了一种时间延迟发生器200的装置和方法。 该装置包括时间延迟门212，混频器216（吉尔伯特单元电路）和当前的数模转换器206。 由第一和第二晶体管差分对218和220组成的混频器216接收模拟输入信号202而没有延迟，以及由时间门延迟产生的延迟的输入信号210。 数模转换器调节第一控制信号232和第二控制信号238之间的相对电流，有效地改变未延迟的输入信号208和延迟输入信号210的混合，以产生具有时间的延迟的输出信号214或 相位延迟基本上等于由数字信号输入204表示的时间延迟。 延时发生器具有降低的相位噪声和线性时间延迟响应。