公开(公告)号：US20060219893A1

公开(公告)日：2006-10-05

申请号：US11271977

申请日：2005-11-14

申请人： Ken Nishihira ,  Kageyoshi Katakura ,  Shigeru Honjo

发明人： Ken Nishihira ,  Kageyoshi Katakura ,  Shigeru Honjo

IPC分类号： B01D59/44 ,  H01J49/00

CPC分类号： G01N1/2273 ,  G01N2001/022 ,  H01J49/0036

摘要： A standard mass chromatogram which a substance to be detected exhibits is provided as a database within an apparatus. A measured mass chromatogram obtained by measurement and the standard mass chromatogram stored in the database are compared with each other after their standardization to determine the degree of coincidence of the two. Then, by utilizing the degree of coincidence, it is determined whether the substance to be detected has been detected or not. Further, two ions are selected from among plural ions derived from the substance to be detected and correlation between mass chromatograms of the two selected ions is compared with correlation between mass chromatograms of the two selected ions stored in the database to determine the degree of coincidence of the two. This degree of coincidence is also utilized for determining whether the substance to be detected has been detected or not.

摘要翻译： 待检测物质的标准质量色谱图作为设备内的数据库提供。 通过测量获得的测量质量色谱图和数据库中存储的标准质量色谱图在标准化后相互比较，以确定两者的符合程度。 然后，通过利用一致度，确定是否检测到了被检测物质。 此外，从待检测物质中得到的多个离子中选择两个离子，并将两个选择的离子的质谱图之间的相关性与存储在数据库中的两个选定离子的质谱图之间的相关性进行比较，以确定 他们俩。 这种重合度也用于确定是否检测到被检测物质。

公开(公告)号：US07041971B2

公开(公告)日：2006-05-09

申请号：US10644806

申请日：2003-08-21

申请人： Masumi Fukano ,  Shigeru Honjo ,  Hisashi Nagano ,  Yasuaki Takada ,  Yasuo Seto ,  Teruo Itoi ,  Kazumitsu Iura

发明人： Masumi Fukano ,  Shigeru Honjo ,  Hisashi Nagano ,  Yasuaki Takada ,  Yasuo Seto ,  Teruo Itoi ,  Kazumitsu Iura

IPC分类号： H01J49/10

CPC分类号： G01N33/0044 ,  G01N27/68 ,  H01J49/04

摘要： An object of the present invention is to obtain an apparatus and a method for the detection of chemical agents which are suitable for detecting sulfur mustard and lewisite 1 and are satisfactory from the viewpoint of the speed of detection of chemical agents, the reduction of the rate of wrong information, the specification of the kinds of the chemical agents, and an unmanned continuous-monitoring apparatus. In the present invention, the detecting apparatus comprises a sample introduction section 1 into which a sample is introduced to be heated, an ionization section 2 in which the sample from the sample introduction section is ionized, a mass spectrometry section 3, and a computer 6 for data analysis. When predetermined signals characteristic of sulfur mustard or lewisite 1 are observed, it becomes possible to specify the sample.

摘要翻译： 本发明的目的是获得一种适用于检测硫芥和虱子1的化学试剂的检测装置和方法，并且从化学试剂的检测速度的观点来看是令人满意的 错误信息，化学剂种类的规格，以及无人值守的连续监测装置。 在本发明中，检测装置包括：试样导入部1，其中导入待加热的试样，将来自试样导入部的试样离子化的电离部2，质谱分析部3和计算机6 用于数据分析。 当观察到硫芥子或虱子1的特征的预定信号时，可以指定样品。

公开(公告)号：US06943343B2

公开(公告)日：2005-09-13

申请号：US10628139

申请日：2003-07-29

申请人： Shigeru Honjo ,  Yasuaki Takada ,  Hisashi Nagano ,  Masumi Fukano ,  Yasuo Seto ,  Teruo Itoi ,  Kazumitsu Iura ,  Mieko Kataoka ,  Kouichiro Tsuge

发明人： Shigeru Honjo ,  Yasuaki Takada ,  Hisashi Nagano ,  Masumi Fukano ,  Yasuo Seto ,  Teruo Itoi ,  Kazumitsu Iura ,  Mieko Kataoka ,  Kouichiro Tsuge

IPC分类号： G01N27/62 ,  G01N27/64 ,  G01N27/68 ,  H01J49/04 ,  H01J49/10 ,  H01J49/42 ,  B01D59/44

CPC分类号： G01N27/622

摘要： An apparatus for detecting a chemical agent, capable of increasing a detection speed of a chemical agent, decreasing a false alarm rate, pinning down the kind of a chemical agent, and meeting specifications for unattended continuous monitoring equipment suitable for detecting sarin or soman. This detection apparatus comprises a sample introduction unit for introducing a sample, an ionizing unit for positively ionizing the sample from the sample introduction unit, a mass spectrometer unit for analyzing ions of the sample, and a computer for analyzing data, and is best suited for identifying a dangerous substance by detecting signals peculiar to chemical agents, such as sarin or soman.

摘要翻译： 用于检测化学试剂的装置，能够提高化学试剂的检测速度，降低误报率，固定化学试剂的种类，并满足适合于检测沙林或索曼的无人值守连续监测设备的规格。 该检测装置包括用于引入样品的样品引入单元，用于从样品引入单元正电离样品的离子化单元，用于分析样品的离子的质谱仪单元和用于分析数据的计算机，并且最适合于 通过检测诸如沙林或索曼等化学剂特有的信号来识别危险物质。

公开(公告)号：US20050092915A1

公开(公告)日：2005-05-05

申请号：US10644806

申请日：2003-08-21

申请人： Masumi Fukano ,  Shigeru Honjo ,  Hisashi Nagano ,  Yasuaki Takada ,  Yasuo Seto ,  Teruo Itoi ,  Kazumitsu Iura

发明人： Masumi Fukano ,  Shigeru Honjo ,  Hisashi Nagano ,  Yasuaki Takada ,  Yasuo Seto ,  Teruo Itoi ,  Kazumitsu Iura

IPC分类号： G01N27/62 ,  G01N27/68 ,  G01N33/00 ,  H01J49/04 ,  H01J49/00 ,  B01D59/44

CPC分类号： G01N33/0044 ,  G01N27/68 ,  H01J49/04

摘要： An object of the present invention is to obtain an apparatus and a method for the detection of chemical agents which are suitable for detecting sulfur mustard and lewisite 1 and are satisfactory from the viewpoint of the speed of detection of chemical agents, the reduction of the rate of wrong information, the specification of the kinds of the chemical agents, and an unmanned continuous-monitoring apparatus. In the present invention, the detecting apparatus comprises a sample introduction section 1 into which a sample is introduced to be heated, an ionization section 2 in which the sample from the sample introduction section is ionized, a mass spectrometry section 3, and a computer 6 for data analysis. When predetermined signals characteristic of sulfur mustard or lewisite 1 are observed, it becomes possible to specify the sample.

摘要翻译： 本发明的目的是获得一种适用于检测硫芥和虱子1的化学试剂的检测装置和方法，从化学试剂的检测速度，速率的降低的观点来看是令人满意的 错误信息，化学剂种类的规格，以及无人值守的连续监测装置。 在本发明中，检测装置包括：试样导入部1，其中导入待加热的试样，将来自试样导入部的试样离子化的电离部2，质谱分析部3和计算机6 用于数据分析。 当观察到硫芥子或虱子1的特征的预定信号时，可以指定样品。

公开(公告)号：US5146427A

公开(公告)日：1992-09-08

申请号：US825782

申请日：1992-01-21

申请人： Katsuro Sasaki ,  Nobuyuki Moriwaki ,  Shigeru Honjo ,  Hideaki Nakamura

发明人： Katsuro Sasaki ,  Nobuyuki Moriwaki ,  Shigeru Honjo ,  Hideaki Nakamura

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1051

摘要： In a semiconductor memory, a latch circuit is arranged between the outputs of a sense amplifier and the inputs of a data output buffer. First pass-gates are arranged between the outputs of the sense amplifier and the latch circuit, while second pass-gates are arranged between the latch circuit and the inputs of the data output buffer. The outputs of the sense amplifier are transmitted to the inputs of the data output buffer through signal paths which bypass the first pass-gates, the latch circuit and the second pass-gates, whereby the data output buffer generates a data output quickly. Thereafter, the first pass-gates and the second pass-gates are controllably brought to a signal-through condition, whereby the output information items of the sense amplifier are stored in the latch circuit. The data output buffer holds the data output in conformity with the stored information items of the latch circuit. For a period of time for which the data output buffer holds the data output, the sense amplifier is held in a non-activated condition, so that the power consumption of the semiconductor memory is lowered.

摘要翻译： 在半导体存储器中，锁存电路布置在读出放大器的输出端和数据输出缓冲器的输入端之间。 第一通过门被布置在读出放大器和锁存电路的输出之间，而第二通过门被布置在锁存电路和数据输出缓冲器的输入之间。 读出放大器的输出通过旁路第一通过门，锁存电路和第二传递门的信号路径被发送到数据输出缓冲器的输入，从而数据输出缓冲器快速产生数据输出。 此后，第一通过门和第二通过门被可控地带到信号通过状态，由此将读出放大器的输出信息项存储在锁存电路中。 数据输出缓冲器保存符合存储的锁存电路的信息项的数据输出。 在数据输出缓冲器保持数据输出的一段时间内，读出放大器保持在非激活状态，从而降低了半导体存储器的功耗。

公开(公告)号：US5132771A

公开(公告)日：1992-07-21

申请号：US503928

申请日：1990-04-04

申请人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

发明人： Toshiaki Yamanaka ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Akihiro Shimizu ,  Koichiro Ishibashi ,  Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Eiji Takeda ,  Yoshio Sakai ,  Takashi Nishida ,  Osamu Minato ,  Toshiaki Masuhara ,  Shoji Hanamura ,  Shigeru Honjo ,  Nobuyuki Moriwaki

IPC分类号： G11C11/412 ,  H01L27/11

CPC分类号： G11C11/4125 ,  H01L27/1104 ,  Y10S257/903

摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.

摘要翻译： 提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。 半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。 每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。 两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极 另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。 此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以 彼此平行。

公开(公告)号：US5715190A

公开(公告)日：1998-02-03

申请号：US658081

申请日：1996-06-04

申请人： Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

发明人： Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105

CPC分类号： G11C11/22

摘要： A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or an NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.

摘要翻译： 存储矩阵，其包括以矩阵排列的每个由铁电电容器和地址选择MOSFET构成的存储单元，其被划分为多个存储块。 每个存储块设置有模式存储电路，其针对每个存储块以一对应的对应关系存储DRAM模式（易失性模式）或NV模式（非易失性模式），并且利用刷新操作计数电路 每个内存块对连续执行刷新操作的次数进行计数。 在第n次刷新操作（其中n是预定次数）的情况下，进行存储器访问以将铁电电容器的板电压从一个电压临时地改变为另一个电压，同时模式存储电路从 DRAM模式为NV模式。 当执行对存储器块中的存储单元的读取或写入操作时，模式存储电路从NV模式改变为DRAM模式。 根据模式存储电路中存储的信息，对于被设置为NV模式的存储器块，省略刷新操作。

公开(公告)号：US5396100A

公开(公告)日：1995-03-07

申请号：US861366

申请日：1992-03-31

申请人： Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

发明人： Kohji Yamasaki ,  Nobuyuki Moriwaki ,  Shuji Ikeda ,  Hideaki Nakamura ,  Shigeru Honjo

IPC分类号： H01L27/02 ,  H01L27/11 ,  H01L29/76 ,  H01L23/552 ,  H01L27/10

CPC分类号： H01L27/1108 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  Y10S257/903

摘要： Herein disclosed is a semiconductor integrated circuit device which has a memory array or a memory mat formed of memory cells arranged regularly in a matrix shape. At the end portion or inside of the memory array or memory cell in the region of the device where the patterning of the memory cells is discontinued or interrupted, the shape of an element isolating insulating film, which is formed for regulating the memory cells having pattern interruptions, is made substantially identical to the shape of the element isolating insulating film for regulating the memory cells in the region of the device where the patternings of the memory cells are of an uninterrupted regular form. In the location on the chip front face where the regular patterns associated with the memory area are discontinued, there is formed a dummy pattern having a shape made substantially identical to that of a gate electrode arranged at the end portion of the location where the regular patterns are interrupted.

摘要翻译： 这里公开了一种半导体集成电路器件，其具有由矩阵形状规则地排列的存储单元形成的存储器阵列或存储器垫。 在存储器单元的图案化中断或中断的器件的区域中的存储器阵列或存储单元的端部或内部，形成用于调节具有图案的存储单元的元件隔离绝缘膜的形状 使得与存储单元的图形不间断规则形式的装置区域中用于调节存储单元的元件隔离绝缘膜的形状基本相同。 在与存储区域相关联的规则图案的芯片正面上的位置中断的情况下，形成具有与布置在位置的端部的栅电极的形状基本相同的形状的虚设图案，其中规则图案 被中断。

公开(公告)号：US5528535A

公开(公告)日：1996-06-18

申请号：US399511

申请日：1995-03-07

申请人： Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

发明人： Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

IPC分类号： G11C14/00 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  G11C11/406

CPC分类号： G11C11/22

摘要： A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.

摘要翻译： 存储矩阵，其包括以矩阵排列的每个由铁电电容器和地址选择MOSFET构成的存储单元，其被划分为多个存储块。 每个存储块设置有模式存储电路，其针对每个存储块以一对应的对应关系存储DRAM模式（易失性模式）或NV模式（非易失性模式），并且利用刷新操作计数电路 对每个内存块进行连续执行刷新操作的次数。 在第n次刷新操作（其中n是预定次数）的情况下，进行存储器访问以将铁电电容器的板电压从一个电压临时地改变为另一个电压，同时模式存储电路从 DRAM模式为NV模式。 当执行对存储器块中的存储单元的读取或写入操作时，模式存储电路从NV模式改变为DRAM模式。 根据模式存储电路中存储的信息，对于被设置为NV模式的存储器块，省略刷新操作。

公开(公告)号：US4391658A

公开(公告)日：1983-07-05

申请号：US329060

申请日：1981-12-09

申请人： Syoiti Kitane ,  Shigeru Honjo ,  Kuniyoshi Ohe ,  Fumio Tobioka

发明人： Syoiti Kitane ,  Shigeru Honjo ,  Kuniyoshi Ohe ,  Fumio Tobioka

IPC分类号： H01L29/73 ,  H01L21/02 ,  H01L21/22 ,  H01L21/225 ,  H01L21/331

CPC分类号： H01L21/2252

摘要： A method for manufacturing a semiconductor substrate comprising the steps of forming on all surfaces of a raw semiconductor substrate an impurity layer of the same conductivity type as the raw semiconductor substrate and forming a first insulating film on the entire impurity layer, removing those portions of the impurity layer and first insulating film which are formed on one major surface of the raw semiconductor substrate and finishing the exposed major surface of the raw semiconductor substrate, thus providing a mirror surface, forming a second insulating film on the mirror surface of the raw semiconductor substrate and on the remaining first insulating film, forming a protective film on the entire second insulating film and forming a third insulating film on the entire protective film, thus providing a laminate, holding the laminate side by side together with other laminates provided in the same way, heating the laminates thus held, in an oxidizing atmosphere, thereby diffusing the impurity from the impurity layers into the raw semiconductor substrates to form diffusion layers in the raw semiconductor substrates, and removing the first insulating film, second insulating film, protective film and third insulating film from each of the laminates. According to the invention, a high precision and high quality product semiconductor substrate can be inexpensively provided.

摘要翻译： 一种制造半导体衬底的方法，包括以下步骤：在原始半导体衬底的所有表面上形成与原始半导体衬底相同导电类型的杂质层，并在整个杂质层上形成第一绝缘膜，除去 杂质层和第一绝缘膜，其形成在原料半导体衬底的一个主表面上，并且对原始半导体衬底的暴露的主表面进行精加工，从而提供镜面，在原料半导体衬底的镜面上形成第二绝缘膜 并且在剩余的第一绝缘膜上，在整个第二绝缘膜上形成保护膜，并在整个保护膜上形成第三绝缘膜，从而提供层叠体，将层叠体与以相同方式设置的其它层压体并排地保持 ，在氧化气氛中加热由此保持的层压体，由此扩散 从杂质层向原料半导体衬底中杂质，在原料半导体衬底中形成扩散层，从每个层压体中除去第一绝缘膜，第二绝缘膜，保护膜和第三绝缘膜。 根据本发明，可以廉价地提供高精度和高质量的产品半导体衬底。