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    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
    1.
    发明授权
    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock 有权
    将具有与系统时钟的可选择的相位差的I / O缓冲器与与系统时钟同步的远程I / O缓冲器进行时钟

    公开(公告)号：US06748549B1

    公开(公告)日：2004-06-08

    申请号：US09604049

    申请日：2000-06-26

    申请人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    发明人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    IPC分类号： G06F104

    CPC分类号： G01R31/31937

    摘要： Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.

    摘要翻译： 输入/输出（I / O）时钟相位调整电路，用于集成电路芯片的I / O缓冲电路。 在一个实施例中，集成电路芯片包括耦合以接收系统时钟的相位调整电路。 相位调整电路产生I / O时钟，I / O时钟由系统中用于I / O数据传输的集成电路芯片的I / O缓冲电路接收。 相位调整电路包括锁相环（PLL）电路，其被耦合以通过第一延迟电路接收系统时钟。 由PLL电路产生的I / O时钟通过PLL电路的反馈时钟输入端的第二延迟电路接收。 第一和第二延迟电路用于控制PLL电路相对于系统时钟产生的I / O时钟的相位。 在一个实施例中，第三延迟电路包括在集成电路的I / O缓冲电路的I / O数据路径中。 第三延迟电路使得来自集成电路的输入和输出数据传输被实时地与由相位调整电路产生的I / O时钟异相。

    Phase locked loop system capable of deskewing
    2.
    发明授权
    Phase locked loop system capable of deskewing 有权
    锁相环系统能够进行偏斜校正

    公开(公告)号：US07199624B2

    公开(公告)日：2007-04-03

    申请号：US10425914

    申请日：2003-04-30

    申请人： Keng L. Wong ,  Gregory F. Taylor ,  Chee How Lim

    发明人： Keng L. Wong ,  Gregory F. Taylor ,  Chee How Lim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/081 ,  G06F1/10 ,  H03L7/087 ,  H03L7/235 ,  H03L2207/04

    摘要： A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.

    摘要翻译： 提供了一种系统，其包括基于参考时钟信号和反馈时钟信号输出第一信号的锁相环组件。 时钟分配网络可以基于从锁相环组件输出的第一信号来分配时钟信号。 此外，延迟锁定环路分量可能会使信号产生偏斜，并调整由时钟分配网络分配的时钟信号。

    Multi-loop circuit capable of providing a delayed clock in phase locked loops
    3.
    发明授权
    Multi-loop circuit capable of providing a delayed clock in phase locked loops 失效
    能够在锁相环中提供延迟时钟的多回路电路

    公开(公告)号：US07184503B2

    公开(公告)日：2007-02-27

    申请号：US11303682

    申请日：2005-12-15

    申请人： Keng L. Wong ,  Chee How Lim

    发明人： Keng L. Wong ,  Chee How Lim

    IPC分类号： H04L7/00 ,  H03L7/06 ,  H03D3/24

    CPC分类号： H03L7/0891 ,  H03L7/095

    摘要： A multi-loop circuit includes a first switching device to receive a first clock pulse and a second delayed pulse and produce a first output pulse including either the first clock pulse or the second delayed pulse. A first delay device receives the first output pulse and produces a first delayed pulse. A second switching device receives a second clock pulse and the first delayed pulse and produces a second output pulse including either the second clock pulse or the first delayed pulse. A second delay device receives the second output pulse and produces the second delayed pulse. A third switching device receives the first and second delayed pulses and produces a first output signal. A fourth switching device receives the first and second delayed pulses and produces a second output signal. A controller is coupled to control the first, second, third, and fourth switching devices.

    摘要翻译： 多回路电路包括用于接收第一时钟脉冲和第二延迟脉冲并产生包括第一时钟脉冲或第二延迟脉冲的第一输出脉冲的第一开关器件。 第一延迟装置接收第一输出脉冲并产生第一延迟脉冲。 第二开关装置接收第二时钟脉冲和第一延迟脉冲，并产生包括第二时钟脉冲或第一延迟脉冲的第二输出脉冲。 第二延迟装置接收第二输出脉冲并产生第二延迟脉冲。 第三开关装置接收第一和第二延迟脉冲并产生第一输出信号。 第四开关装置接收第一和第二延迟脉冲并产生第二输出信号。 控制器被耦合以控制第一，第二，第三和第四开关装置。

    Cascaded phase-locked loops
    4.
    发明授权
    Cascaded phase-locked loops 有权
    级联锁相环

    公开(公告)号：US06842056B1

    公开(公告)日：2005-01-11

    申请号：US10603722

    申请日：2003-06-24

    申请人： Keng L. Wong ,  Cangsang Zhao ,  Chee How Lim

    发明人： Keng L. Wong ,  Cangsang Zhao ,  Chee How Lim

    IPC分类号： G06F1/04 ,  H03L7/00 ,  H03L7/06 ,  H03L7/089 ,  H03L7/23

    CPC分类号： G06F1/04 ,  H03L7/0891 ,  H03L7/23

    摘要： A method and apparatus for generating clock frequencies using cascaded phase-locked loop (PLL) circuits includes a first PLL circuit coupled to a second PLL circuit to produce a microprocessor I/O data clock signal and a microprocessor core clock signal, respectively. In one embodiment, the first PLL produces the data clock signal based upon a first reference signal and a first feedback signal, where the first feedback signal is derived from the data clock signal. Furthermore, the second PLL circuit produces the core clock signal based at least in part upon a second reference signal and a second feedback signal, where the second reference signal is derived from the data clock signal and the second feedback signal is derived from the core clock signal.

    摘要翻译： 使用级联锁相环（PLL）电路产生时钟频率的方法和装置包括分别耦合到第二PLL电路以产生微处理器I / O数据时钟信号和微处理器核心时钟信号的第一PLL电路。 在一个实施例中，第一PLL基于第一参考信号和第一反馈信号产生数据时钟信号，其中从数据时钟信号导出第一反馈信号。 此外，第二PLL电路至少部分地基于第二参考信号和第二反馈信号产生核心时钟信号，其中第二参考信号从数据时钟信号导出，并且第二反馈信号从核心时钟导出 信号。

    Method and apparatus for jitter reduction in phase locked loops
    5.
    发明授权
    Method and apparatus for jitter reduction in phase locked loops 失效

    公开(公告)号：US07023945B2

    公开(公告)日：2006-04-04

    申请号：US10171597

    申请日：2002-06-17

    申请人： Keng L. Wong ,  Chee How Lim

    发明人： Keng L. Wong ,  Chee How Lim

    IPC分类号： H03D3/24 ,  H03L7/06

    CPC分类号： H03L7/0891 ,  H03L7/095

    摘要： A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.

    Method and apparatus for reducing lock time in dual charge-pump phase-locked loops
    6.
    发明授权
    Method and apparatus for reducing lock time in dual charge-pump phase-locked loops 有权
    减少双电荷泵锁相环锁定时间的方法和装置

    公开(公告)号：US06937075B2

    公开(公告)日：2005-08-30

    申请号：US10447697

    申请日：2003-05-29

    申请人： Chee How Lim ,  Keng L. Wong ,  Rachael Parker

    发明人： Chee How Lim ,  Keng L. Wong ,  Rachael Parker

    IPC分类号： H03L7/089 ,  H03L7/093 ,  H03L7/107 ,  H03L7/06

    CPC分类号： H03L7/107 ,  H03L7/0893 ,  H03L7/093 ,  H03L7/1072 ,  H03L2207/06

    摘要： A phase-locked loop includes a phase detector to measure a phase offset between a reference clock signal and a feedback clock signal, and to generate first and second output control signals having a pulse width corresponding to the phase offset. The phase locked loop further includes a first pulse width control circuit coupled to the phase detector to reduce the pulse width of the first output control signal producing a first modified output control signal, a second pulse width control circuit coupled to the phase detector to reduce the pulse width of the second output control signal producing a second modified output control signal, a first charge pump coupled to the phase detector to provide a first charge signal responsive to the first and second output control signals, and a second charge pump coupled to the first and second pulse width control circuits to provide a second charge signal responsive to the first and second modified output control signals.

    摘要翻译： 锁相环包括用于测量参考时钟信号和反馈时钟信号之间的相位偏移的相位检测器，并且产生具有对应于相位偏移的脉冲宽度的第一和第二输出控制信号。 锁相环还包括耦合到相位检测器的第一脉冲宽度控制电路，以减小产生第一修改输出控制信号的第一输出控制信号的脉冲宽度，耦合到相位检测器的第二脉宽控制电路， 第二输出控制信号的脉冲宽度产生第二修改输出控制信号，第一电荷泵耦合到相位检测器以响应于第一和第二输出控制信号提供第一电荷信号，以及耦合到第一输出控制信号的第二电荷泵 和第二脉冲宽度控制电路，以响应于第一和第二修改的输出控制信号提供第二充电信号。

    Method and apparatus for fast lock acquisition in self-biased phase locked loops
    8.
    发明授权
    Method and apparatus for fast lock acquisition in self-biased phase locked loops 有权
    在自偏置锁相环中快速锁定采集的方法和装置

    公开(公告)号：US06919769B2

    公开(公告)日：2005-07-19

    申请号：US10670828

    申请日：2003-09-24

    申请人： Chee How Lim ,  Keng L. Wong

    发明人： Chee How Lim ,  Keng L. Wong

    IPC分类号： H03B1/00 ,  H03L7/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/10 ,  H03L7/113 ,  H03L7/18

    CPC分类号： H03L7/113 ,  H03L7/0891 ,  H03L7/18

    摘要： A self-biased phase locked loop (PLL) circuit includes a charge pump to generate a control voltage, a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage, discharge circuitry coupled to the charge pump to discharge the control voltage, and frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.

    摘要翻译： 自偏置锁相环（PLL）电路包括电荷泵以产生控制电压，耦合到电荷泵的受控振荡器至少部分地基于控制电压产生输出信号，耦合到电荷的放电电路 泵以释放控制电压，以及耦合到受控振荡器和放电电路的频率检测电路，以产生数字反馈信号，用于当输出信号达到阈值频率时终止放电电路对控制电压的放电，阈值频率为 目标频率。

    Global I/O timing adjustment using calibrated delay elements
    9.
    发明授权
    Global I/O timing adjustment using calibrated delay elements 有权
    使用校准延迟元件的全局I / O定时调整

    公开(公告)号：US07197659B2

    公开(公告)日：2007-03-27

    申请号：US09965223

    申请日：2001-09-28

    申请人： Chee How Lim ,  Keng L. Wong ,  Songmin Kim

    发明人： Chee How Lim ,  Keng L. Wong ,  Songmin Kim

    IPC分类号： G06F1/12

    CPC分类号： H03L7/0812 ,  G06F1/10 ,  H03L7/07

    摘要： A method transfers a signal from a transmitting device to a receiving device. The signal is output from the transmitting device using a driving circuit. A reference clock signal is received in the transmitting device. An output clock signal is generated according to the received reference clock signal and a feedback clock signal in a phase locked loop. A delay is provided in a path of the reference clock signal and a path of the feedback clock signal. The delay is configured to make the output signal meet a predetermined valid data timing requirement.

    摘要翻译： 一种方法将信号从发送设备传送到接收设备。 使用驱动电路从发送装置输出信号。 在发送装置中接收参考时钟信号。 根据接收的参考时钟信号和锁相环中的反馈时钟信号产生输出时钟信号。 在参考时钟信号的路径和反馈时钟信号的路径中提供延迟。 延迟被配置为使输出信号满足预定的有效数据时序要求。