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    Phase locked loop system capable of deskewing
    1.
    发明授权
    Phase locked loop system capable of deskewing 有权
    锁相环系统能够进行偏斜校正

    公开(公告)号：US07199624B2

    公开(公告)日：2007-04-03

    申请号：US10425914

    申请日：2003-04-30

    申请人： Keng L. Wong ,  Gregory F. Taylor ,  Chee How Lim

    发明人： Keng L. Wong ,  Gregory F. Taylor ,  Chee How Lim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/081 ,  G06F1/10 ,  H03L7/087 ,  H03L7/235 ,  H03L2207/04

    摘要： A system is provided that includes a phase lock loop component to output a first signal based on a reference clock signal and a feedback clock signal. A clock distribution network may distribute a clock signal based on the first signal output from the phase lock loop component. Additionally, a delay lock loop component may deskew a signal and adjust the clock signal distributed by the clock distribution network.

    摘要翻译： 提供了一种系统，其包括基于参考时钟信号和反馈时钟信号输出第一信号的锁相环组件。 时钟分配网络可以基于从锁相环组件输出的第一信号来分配时钟信号。 此外，延迟锁定环路分量可能会使信号产生偏斜，并调整由时钟分配网络分配的时钟信号。

    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
    2.
    发明授权
    Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock 有权
    将具有与系统时钟的可选择的相位差的I / O缓冲器与与系统时钟同步的远程I / O缓冲器进行时钟

    公开(公告)号：US06748549B1

    公开(公告)日：2004-06-08

    申请号：US09604049

    申请日：2000-06-26

    申请人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    发明人： Chi-Yeu Chao ,  Chee How Lim ,  Keng L. Wong ,  Songmin Kim ,  Gregory F. Taylor

    IPC分类号： G06F104

    CPC分类号： G01R31/31937

    摘要： Input/output (I/O) clock phase adjustment circuitry for use with I/O buffer circuitry of an integrated circuit chip. In one embodiment, an integrated circuit chip includes a phase adjustment circuit coupled to receive a system clock. The phase adjustment circuit generates an I/O clock coupled to be received by an I/O buffer circuit of an integrated circuit chip for I/O data transfers in a system. The phase adjustment circuit includes a phase locked loop (PLL) circuit coupled to receive the system clock through a first delay circuit. The I/O clock generated by the PLL circuit is received through a second delay circuit at a feedback clock input of the PLL circuit. The first and second delay circuits are used to control the phase of the I/O clock generated by the PLL circuit relative to the system clock. In one embodiment, a third delay circuit is included in an I/O data path of the I/O buffer circuit of the integrated circuit. The third delay circuit enables input and output data transmissions from the integrated circuit to be clocked, in effect, out of phase with the I/O clock generated by phase adjustment circuit.

    摘要翻译： 输入/输出（I / O）时钟相位调整电路，用于集成电路芯片的I / O缓冲电路。 在一个实施例中，集成电路芯片包括耦合以接收系统时钟的相位调整电路。 相位调整电路产生I / O时钟，I / O时钟由系统中用于I / O数据传输的集成电路芯片的I / O缓冲电路接收。 相位调整电路包括锁相环（PLL）电路，其被耦合以通过第一延迟电路接收系统时钟。 由PLL电路产生的I / O时钟通过PLL电路的反馈时钟输入端的第二延迟电路接收。 第一和第二延迟电路用于控制PLL电路相对于系统时钟产生的I / O时钟的相位。 在一个实施例中，第三延迟电路包括在集成电路的I / O缓冲电路的I / O数据路径中。 第三延迟电路使得来自集成电路的输入和输出数据传输被实时地与由相位调整电路产生的I / O时钟异相。

    Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
    3.
    发明授权
    Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation 有权
    在主从配置中使用单个参考组件进行多电路补偿的装置和方法

    公开(公告)号：US06717455B2

    公开(公告)日：2004-04-06

    申请号：US10338233

    申请日：2003-01-08

    申请人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Songmin Kim ,  Gregory F. Taylor

    发明人： Usman A. Mughal ,  Razi Uddin ,  Chee How Lim ,  Songmin Kim ,  Gregory F. Taylor

    IPC分类号： H03K1714

    CPC分类号： H03K19/00384

    摘要： A single external impedance element is used to perform multiple circuit compensation. A reference impedance code is first generated from a master circuit, and then the reference impedance code is shifted to generate a slave impedance code. The slave impedance code is provided to one or more slave circuits to activate devices in the slave circuit(s). Impedance-generation devices coupled to the slave circuit are then activated one at a time until their generated impedance corresponds to the impedance generated by the slave circuit. The reference impedance code can be incremented or decremented (e.g., shifted) to generate slave impedance codes corresponding to different impedance values, according to impedance requirements of various different circuits that require compensation.

    摘要翻译： 单个外部阻抗元件用于执行多路电路补偿。 首先从主电路产生参考阻抗代码，然后偏移参考阻抗代码以产生从阻抗代码。 从属阻抗码被提供给一个或多个从属电路以激活从属电路中的设备。 耦合到从电路的阻抗发生器件然后一次被激活，直到其产生的阻抗对应于由从电路产生的阻抗。 根据需要补偿的各种不同电路的阻抗要求，参考阻抗代码可以递增或递减（例如移位）以产生对应于不同阻抗值的从属阻抗代码。

    On-chip termination
    4.
    发明授权
    On-chip termination 有权
    片上终止

    公开(公告)号：US6157206A

    公开(公告)日：2000-12-05

    申请号：US224369

    申请日：1998-12-31

    申请人： Gregory F. Taylor ,  Jack A. Price ,  Chee How Lim

    发明人： Gregory F. Taylor ,  Jack A. Price ,  Chee How Lim

    IPC分类号： H03H11/28 ,  H03H11/30 ,  H04L25/02 ,  H03K17/16 ,  H03K19/0185

    CPC分类号： H03H11/30

    摘要： Integrated circuits include an impedance control circuit having at least one output terminal coupled to an on-chip reference termination device in order to control output impedance of the reference termination device such that it matches that of an external resistance. The impedance control circuit outputs are also coupled to the on-chip impedance-controlled termination devices which are coupled to each of the external transmission lines to be terminated. In this way, a single reference resistance allows many transmission lines to be properly terminated. The impedance-controlled termination devices are may be implemented as pairs of binary weighted p-channel and n-channel field effect transistors.

    摘要翻译： 集成电路包括阻抗控制电路，其具有耦合到片上参考终端设备的至少一个输出端子，以便控制参考端接装置的输出阻抗，使得其匹配外部电阻的输出阻抗。 阻抗控制电路输出还耦合到片上阻抗控制的终端设备，其被耦合到要终止的每个外部传输线。 以这种方式，单个参考电阻允许许多传输线被适当地终止。 阻抗控制终端装置可以被实现为二进制加权p沟道和n沟道场效应晶体管的对。

    Internal clock jitter detector
    6.
    发明授权
    Internal clock jitter detector 有权
    内部时钟抖动检测器

    公开(公告)号：US06208169B1

    公开(公告)日：2001-03-27

    申请号：US09340975

    申请日：1999-06-28

    申请人： Keng L. Wong ,  Gregory F. Taylor ,  Ravishankar Kuppuswamy ,  Douglas R. Parker ,  Hung-Piao Ma ,  Kent R. Callahan ,  Xia Dai

    发明人： Keng L. Wong ,  Gregory F. Taylor ,  Ravishankar Kuppuswamy ,  Douglas R. Parker ,  Hung-Piao Ma ,  Kent R. Callahan ,  Xia Dai

    IPC分类号： H03K19096

    CPC分类号： H03L7/091 ,  H03L7/0814

    摘要： An apparatus and method for detecting and measuring internal clock jitter is disclosed. In one embodiment, a reference clock generator generates a reference clock signal based on an instantaneous clock signal. The reference clock signal includes the instantaneous clock signal delayed for an average duration. A phase comparing element receives both the instantaneous clock signal and the reference clock signal such that the phase comparing element measures a phase difference between the instantaneous clock signal and the reference clock signal. The magnitude and direction of the phase difference is indicated by one of a number of distinct phase difference bins in the phase comparing element.

    摘要翻译： 公开了一种用于检测和测量内部时钟抖动的装置和方法。 在一个实施例中，参考时钟发生器基于瞬时时钟信号产生参考时钟信号。 参考时钟信号包括延迟平均持续时间的瞬时时钟信号。 相位比较元件接收瞬时时钟信号和参考时钟信号，使得相位比较元件测量瞬时时钟信号和参考时钟信号之间的相位差。 相位差的幅度和方向由相位比较元件中的多个不同的相位差区之一表示。

    Power-on initializing circuit
    7.
    发明授权
    Power-on initializing circuit 失效
    上电初始化电路

    公开(公告)号：US5801561A

    公开(公告)日：1998-09-01

    申请号：US842501

    申请日：1997-04-21

    申请人： Keng L. Wong ,  Gregory F. Taylor ,  Roshan J. Fernando ,  Jeffrey E. Smith

    发明人： Keng L. Wong ,  Gregory F. Taylor ,  Roshan J. Fernando ,  Jeffrey E. Smith

    IPC分类号： H03K17/22

    CPC分类号： H03K17/22

    摘要： A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.

    摘要翻译： 一种减少上电期间集成电路竞争的方法和装置。 根据本发明的一个方面，在集成电路中包括初始化电路。 响应于接收到Vcc，初始化电路产生替代时钟信号和替代复位信号。 替代时钟信号和替代复位信号在上电期间代替芯片内产生的时钟信号和芯片外产生的复位信号，直到满足预定条件。 响应于接收到替代时钟信号和替代复位信号，初始化所述集成电路上的多个电路。

    Fuse cell array with redundancy features
    8.
    发明申请
    Fuse cell array with redundancy features 有权
    具有冗余特性的保险丝座阵列

    公开(公告)号：US20080151593A1

    公开(公告)日：2008-06-26

    申请号：US11644381

    申请日：2006-12-22

    申请人： Zhanping Chen ,  Jonathan P. Douglas ,  Praveen Mosalikanti ,  Kevin Zhang ,  Gregory F. Taylor

    发明人： Zhanping Chen ,  Jonathan P. Douglas ,  Praveen Mosalikanti ,  Kevin Zhang ,  Gregory F. Taylor

    IPC分类号： G11C17/16

    CPC分类号： G11C17/16 ,  G11C17/14 ,  G11C17/18 ,  G11C29/816

    摘要： An apparatus, a method, and a system for a fuse cell array are disclosed herein. A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

    摘要翻译： 本文公开了一种用于熔丝单元阵列的装置，方法和系统。 多个熔丝单元被布置成阵列。 一个或多个保险丝单元包括分别输出一对电压的一对熔丝器件，其中该对熔丝器件被冗余编程。 感测放大器耦合到多个熔丝单元以分别从多个熔丝单元中的每一个读出一对电压输出。 比较器电路耦合到读出放大器以比较多个熔丝单元中的每一个的一对电压输出并输出比较结果。

    Method and apparatus for voltage-mode differential simultaneous bi-directional signaling
    10.
    发明授权
    Method and apparatus for voltage-mode differential simultaneous bi-directional signaling 有权
    用于电压模式差分同步双向信令的方法和装置

    公开(公告)号：US06573764B1

    公开(公告)日：2003-06-03

    申请号：US09963037

    申请日：2001-09-24

    申请人： Gregory F. Taylor

    发明人： Gregory F. Taylor

    IPC分类号： H03K190175

    CPC分类号： H04L25/0292 ,  H04L25/0266 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/085

    摘要： A driver/receiver circuit for use at one end of a simultaneous bi-directional differential signal line while being driven at the other end by a similar circuit. The driver/receiver circuit includes a differential driver, a differential receiver, an isolation circuit and an offset generator. The differential driver drives differential signal lines as a function of an output signal. The differential amplifier detects the differential voltage across the differential signal lines via the isolation circuit. The offset generator circuit receives the output signal and, in response, adds an offset to the input terminals of the differential amplifier. The offset cancels at least a portion of the differential voltage across the input terminals of the differential amplifier that results from the DOUT signal. The isolation circuit prevents the offset from significantly affecting the voltage across the differential signal lines.

    摘要翻译： 在同时双向差分信号线的一端使用的驱动器/接收器电路，同时在另一端由相似的电路驱动。 驱动器/接收器电路包括差分驱动器，差分接收器，隔离电路和偏移发生器。 差分驱动器驱动差分信号线作为输出信号的函数。 差分放大器通过隔离电路检测差分信号线两端的差分电压。 偏移发生器电路接收输出信号，作为响应，向差分放大器的输入端添加偏移。 该偏移抵消由DOUT信号产生的差分放大器的输入端上的差分电压的至少一部分。 隔离电路防止偏移显着影响差分信号线两端的电压。